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| DS312 (v3.8) august 26, 2009 www.xilinx.com 1 ? 2005?2009 xilinx, inc. xilinx, the xilinx logo, virtex, spartan, ise, and other designated brands included herein are tradema rks of xilinx in the united states and other coun- tries. all other trademarks are the property of their respective owners. module 1: spartan-3e fpga family: introduction and ordering information DS312-1 (v3.8) august 26, 2009 ? introduction ?features ? architectural overview ? package marking ? ordering information module 2: functional description DS312-2 (v3.8) august 26, 2009 ? input/output blocks (iobs) - overview - selectio? signal standards ? configurable logic block (clb) ? block ram ? dedicated multipliers ? digital clock manager (dcm) ? clock network ? configuration ? powering spartan?-3e fpgas ? production stepping module 3: dc and switching characteristics DS312-3 (v3.8) august 26, 2009 ? dc electrical characteristics - absolute maximum ratings - supply voltage specifications - recommended operating conditions - dc characteristics ? switching characteristics - i/o timing - slice timing -dcm timing -block ram timing - multiplier timing - configuration and jtag timing module 4: pinout descriptions DS312-4 (v3.8) august 26, 2009 ? pin descriptions ? package overview ?pinout tables ? footprint diagrams 0 spartan-3e fpga family: data sheet DS312 (v3.8) august 26, 2009 00 product specification r
spartan-3e fpga family: data sheet 2 www.xilinx.com DS312 (v3.8) august 26, 2009 product specification r DS312-1 (v3.8) august 26, 2009 www.xilinx.com 3 product specification ? 2005?2009 xilinx, inc. xilinx, the xilinx logo, virtex, spartan, ise, and other designated brands included herein are tradema rks of xilinx in the united states and other coun- tries. all other trademarks are the property of their respective owners. introduction the spartan?-3e family of field-programmable gate arrays (fpgas) is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applica- tions. the five-member family offers densities ranging from 100,000 to 1.6 million system gates, as shown in ta bl e 1 . the spartan-3e family builds on the success of the earlier spartan-3 family by increasing the amount of logic per i/o, significantly reducing the cost per logic cell. new features improve system performance and reduce the cost of config- uration. these spartan-3e fpga enhancements, com- bined with advanced 90 nm process technology, deliver more functionality and bandwidth per dollar than was previ- ously possible, setting new standards in the programmable logic industry. because of their exceptionally low cost, spartan-3e fpgas are ideally suited to a wide range of consumer electronics applications, including broadband access, home network- ing, display/projection, and digital television equipment. the spartan-3e family is a superior alternative to mask pro- grammed asics. fpgas avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional asics. also, fp ga programmability permits design upgrades in the field with no hardware replacement necessary, an impo ssibility with asics. features ? very low cost, high-performance logic solution for high-volume, consumer-oriented applications ? proven advanced 90-nanometer process technology ? multi-voltage, multi-standard selectio? interface pins - up to 376 i/o pins or 156 differential signal pairs - lvcmos, lvttl, hstl, and sstl single-ended signal standards - 3.3v, 2.5v, 1.8v, 1.5v, and 1.2v signaling - 622+ mb/s data transfer rate per i/o - true lvds, rsds, mini-lvds, differential hstl/sstl differential i/o - enhanced double data rate (ddr) support - ddr sdram support up to 333 mb/s ? abundant, flexible logic resources - densities up to 33,192 logic cells, including optional shift register or distributed ram support - efficient wide mult iplexers, wide logic - fast look-ahead carry logic - enhanced 18 x 18 multipliers with optional pipeline - ieee 1149.1/1532 jtag programming/debug port ? hierarchical selectram? memory architecture - up to 648 kbits of fast block ram - up to 231 kbits of efficient distributed ram ? up to eight digital clock managers (dcms) - clock skew elimination (delay locked loop) - frequency synthesis, multiplication, division - high-resolution phase shifting - wide frequency range (5 mhz to over 300 mhz) ? eight global clocks plus eight additional clocks per each half of device, plus abundant low-skew routing ? configuration interface to industry-standard proms - low-cost, space-saving spi serial flash prom - x8 or x8/x16 parallel nor flash prom - low-cost xilinx? platform flash with jtag ? complete xilinx ise ? and webpack ? software ? microblaze ? and picoblaze ? embedded processor cores ? fully compliant 32-/64-bit 33 mhz pci support (66 mhz in some devices) ? low-cost qfp and bga packaging options - common footprints support easy density migration - pb-free packaging options ? xa automotive version available 8 spartan-3e fpga family: introduction and ordering information DS312-1 (v3.8) august 26, 2009 0 product specification r ta bl e 1 : summary of spartan-3e fpga attributes device system gates equivalent logic cells clb array (one clb = four slices) distributed ram bits ( 1 ) block ram bits ( 1 ) dedicated multipliers dcms maximum user i/o maximum differential i/o pairs rows columns total clbs total slices xc3s100e 100k 2,160 22 16 240 960 15k 72k 4 2 108 40 xc3s250e 250k 5,508 34 26 612 2,448 38k 216k 12 4 172 68 xc3s500e 500k 10,476 46 34 1,164 4,656 73k 360k 20 4 232 92 xc3s1200e 1200k 19,512 60 46 2,168 8,672 136k 504k 28 8 304 124 xc3s1600e 1600k 33,192 76 58 3,688 14,752 231k 648k 36 8 376 156 notes: 1. by convention, one kb is equivalent to 1,024 bits. 4 www.xilinx.com DS312-1 (v3.8) august 26, 2009 product specification r architectural overview the spartan-3e family architecture consists of five funda- mental programmable functional elements: ? configurable logic blocks (clbs) contain flexible look-up tables (luts) that implement logic plus storage elements used as flip-flops or latches. clbs perform a wide variety of logical functions as well as store data. ? input/output blocks (iobs) control the flow of data between the i/o pins and the internal logic of the device. each iob supports bidirectional data flow plus 3-state operation. supports a variety of signal standards, including four high-performance differential standards. double data-rate (ddr) registers are included. ? block ram provides data storage in the form of 18-kbit dual-port blocks. ? multiplier blocks accept two 18-bit binary numbers as inputs and calculate the product. ? digital clock manager (dcm) blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase-shifting clock signals. these elements are organized as shown in figure 1 . a ring of iobs surrounds a regular array of clbs. each device has two columns of block ram except for the xc3s100e, which has one column. each ram column consists of several 18-kbit ram blocks. each block ram is associated with a dedicated multiplier. the dcms are positioned in the center with two at the top and two at the bottom of the device. the xc3s100e has only one dcm at the top and bottom, while the xc3s1200e and xc3s1600e add two dcms in the middle of the left and right sides. the spartan-3e family features a rich network of traces that interconnect all five functional elements, transmitting sig- nals among them. each functional element has an associ- ated switch matrix that permit s multiple connections to the routing. figure 1: spartan-3e family architecture notes: 1. the xc3s1200e and xc3s1600e have two additional dcms on both the left and right sides as indicated by the dashed lines. the xc3s100e has only one dcm at the top and one at the bottom. DS312-1 (v3.8) august 26, 2009 www.xilinx.com 5 product specification r configuration spartan-3e fpgas are programmed by loading configura- tion data into robust, reprogrammable, static cmos config- uration latches (ccls) that co llectively control all functional elements and routing resources. the fpga?s configuration data is stored externally in a prom or some other non-vol- atile medium, either on or off the board. after applying power, the configuration data is written to the fpga using any of seven different modes: ? master serial from a xilinx platform flash prom ? serial peripheral interface (spi) from an industry-standard spi serial flash ? byte peripheral interface (bpi) up or down from an industry-standard x8 or x8/x16 parallel nor flash ? slave serial, typically downloaded from a processor ? slave parallel, typically downloaded from a processor ? boundary scan (jtag), typically downloaded from a processor or system tester. furthermore, spartan-3e fpgas support multiboot config- uration, allowing two or more fpga configuration bit- streams to be stored in a si ngle parallel nor flash. the fpga application controls which configuration to load next and when to load it. i/o capabilities the spartan-3e fpga selectio interface supports many popular single-ended and differential standards. ta b l e 2 shows the number of user i/os as well as the number of dif- ferential i/o pairs available fo r each device/package combi- nation. spartan-3e fpgas support the following single-ended standards: ? 3.3v low-voltage ttl (lvttl) ? low-voltage cmos (lvcmos) at 3.3v, 2.5v, 1.8v, 1.5v, or 1.2v ? 3v pci at 33 mhz, and in some devices, 66 mhz ? hstl i and iii at 1.8v, commonly used in memory applications ? sstl i at 1.8v and 2.5v, commonly used for memory applications spartan-3e fpgas support the following differential stan- dards: ?lvds ?bus lvds ? mini-lvds ?rsds ? differential hstl (1.8v, types i and iii) ? differential sstl (2.5v and 1.8v, type i) ? 2.5v lvpecl inputs ta bl e 2 : available user i/os and differential (diff) i/o pairs package vq100 vqg100 cp132 cpg132 tq144 tqg144 pq208 pqg208 ft256 ftg256 fg320 fgg320 fg400 fgg400 fg484 fgg484 size (mm) 16x16 8x8 22x22 28x28 17x17 19x19 21x21 23x23 device user diff user diff user diff user diff user diff user diff user diff user diff xc3s100e 66 (7) 30 (2) 83 (11) 35 (2) 108 (28) 40 (4) - - - - - - - - - - xc3s250e 66 (7) 30 (2) 92 (7) 41 (2) 108 (28) 40 (4) 158 (32) 65 (5) 172 (40) 68 (8) - - - - - - xc3s500e 66 (3) (7) 30 (2) 92 (7) 41 (2) - - 158 (32) 65 (5) 190 (41) 77 (8) 232 (56) 92 (12) - - - - xc3s1200e - - - - - - - - 190 (40) 77 (8) 250 (56) 99 (12) 304 (72) 124 (20) - - xc3s1600e - - - - - - - - - - 250 (56) 99 (12) 304 (72) 124 (20) 376 (82) 156 (21) notes: 1. all spartan-3e devices provided in the same package ar e pin-compatible as further described in module 4: pinout descriptions . 2. the number shown in bold indicates the maximum number of i/o and input-only pins. the number shown in ( italics ) indicates the number of input-only pins. 3. the xc3s500e is available in the vqg100 pb-free package and not the standard vq100. the vqg100 and vq100 pin-outs are identic al and general references to the vq100 will apply to the xc3s500e. 6 www.xilinx.com DS312-1 (v3.8) august 26, 2009 product specification r package marking figure 2 provides a top marking example for spartan-3e fpgas in the quad-flat packages. figure 3 shows the top marking for spartan-3e fpgas in bga packages except the 132-ball chip-scale package (cp132 and cpg132). the markings for the bga packages are nearly identical to those for the quad-flat packages, except that the marking is rotated with respect to the ball a1 indicator. figure 4 shows the top marking for spartan-3e fpgas in the cp132 and cpg132 packages. on the qfp and bga packages, the optional numerical stepping code follows the lot code. the ? 5c ? and ? 4i ? part combinations can have a dual mark of ? 5c/4i ?. devices with a single mark are only guaranteed for the marked speed grade and temperature range. all ? 5c ? and ? 4i ? part combinations use the stepping 1 production silicon. figure 2: spartan-3e qfp package marking example stepping code (optional) date code mask revision code process technology xc3s250e tm pq208agq0525 d1234567a 4c spartan device type package speed grade temperature range fabrication code pin p1 r r DS312-1_06_102905 lot code figure 3: spartan-3e bga package marking example lot code date code xc3s250e tm 4c spartan device type bga ball a1 package speed grade temperature range r r DS312-1_02_090105 ft256agq0525 d1234567a mask revision code process code fabrication code stepping code (optional) figure 4: spartan-3e cp132 and cpg132 package marking example date code temperature range speed grade 3s250e c5agq 4c device type ball a1 lot code package c5 = cp132 c6 = cpg132 mask revision code fabrication code DS312-1_05_032105 f1234567-0525 philippines process code DS312-1 (v3.8) august 26, 2009 www.xilinx.com 7 product specification r ordering information spartan-3e fpgas are available in both standard and pb-free packaging options for all device/package combina- tions. all devices are available in pb-free packages, which adds a ?g? character to the ordering code. all devices are available in either commercial (c) or industrial (i) tempera- ture ranges. both the standard ?4 and faster ?5 speed grades are available for the commercial temperature range. however, only the ?4 speed grade is available for the indus- trial temperature range. see ta bl e 2 for valid device/pack- age combinations. production stepping the spartan-3e fpga family uses production stepping to indicate improved capabilities or enhanced features. stepping 1 is, by definition, a functional superset of step- ping 0. furthermore, configuration bitstreams generated for any stepping are forward compatible. see ta b l e 7 2 for addi- tional details. xilinx has shipped both steppi ng 0 and stepping 1. designs operating on the stepping 0 devices perform similarly on a stepping 1 device. stepping 1 devices have been shipping since 2006. the faster speed grade (-5), industrial (i grade), automotive devices, and -4c devices with date codes 0901 (2009) and later, are always stepping 1 devices. only -4c devices have shipped as stepping 0 devices. to specify only the later stepping for the -4c, append an s # suffix to the standard ordering code, where # is the stepping number, as indicated in ta bl e 3 . the stepping level is optionally marked on the device using a single number character, as shown in figure 2 , figure 3 , and figure 4 . xc3s250e -4 ft 256 c de v ice type speed grade temperat u re range package type example: DS312_03_0 8 2409 s1 (optional code to specify stepping 1) nu m b er of pins device speed grade package type / number of pins temperature range (t j ) xc3s100e ?4 standard performance vq100 vqg100 100-pin very thin quad flat pack (vqfp) c commercial (0c to 85c) xc3s250e ?5 high performance cp132 cpg132 132-ball chip-scale package (csp) i industrial (?40c to 100c) xc3s500e tq144 tqg144 144-pin thin quad flat pack (tqfp) xc3s1200e pq208 pqg208 208-pin plastic quad flat pack (pqfp) xc3s1600e ft256 ftg256 256-ball fine-pitch thin ball grid array (ftbga) fg320 fgg320 320-ball fine-pitch ball grid array (fbga) fg400 fgg400 400-ball fine-pitch ball grid array (fbga) fg484 fgg484 484-ball fine-pitch ball grid array (fbga) notes: 1. the ?5 speed grade is exclusively available in the commercial temperature range. 2. the xc3s500e vqg100 is available only in the -4 speed grade. 3. see ds635 for the xa automotive spartan-3e fpgas. ta b l e 3 : spartan-3e optional stepping level ordering stepping number suffix code status 0 none or s0 production 1 s1 production 8 www.xilinx.com DS312-1 (v3.8) august 26, 2009 product specification r revision history the following table shows the revision history for this document. date version revision 03/01/05 1.0 initial xilinx release. 03/21/05 1.1 added xc3s250e in cp132 package to ta b l e 2 . corrected number of differential i/o pairs for cp132 package. added package markings for qfp packages ( figure 2 ) and cp132/cpg132 packages ( figure 4 ). 11/23/05 2.0 added differential hstl and sstl i/o standards. updated ta b l e 2 to indicate number of input-only pins. added production stepping information, including example top marking diagrams. 03/22/06 3.0 upgraded data sheet status to preliminary. added xc3s100e in cp132 package and updated i/o counts for the xc3s1600e in fg320 package ( ta b l e 2 ). added information about dual markings for ?5c and ?4i product combinations to package marking . 11/09/06 3.4 added 66 mhz pci support and links to the xilinx pc i logicore data sheet. indicated that stepping 1 parts are production status. promoted module 1 to production status. synchronized all modules to v3.4. 04/18/08 3.7 added xc3s500e vqg100 package. added reference to xa automotive version. updated links. 08/26/09 3.8 added paragraph to configuration indicating the device supports multiboot configuration. added package sizes to ta b l e 2 . described the speed grade and temperature range guarantee for devices having a single mark in paragraph 3 under package marking . deleted pb-free packaging example under ordering information . revised information under production stepping . revised description of ta bl e 3 . DS312-2 (v3.8) august 26, 2009 www.xilinx.com 9 product specification ? 2005?2009 xilinx, inc. xilinx, the xilinx logo, virtex, spartan, ise, and other designated brands included herein are tradema rks of xilinx in the united states and other coun- tries. all other trademarks are the property of their respective owners. design documentation available the functionality of the spartan?-3e fpga family is now described and updated in the following documents. the topics covered in each guide are listed below. ? ug331: spartan-3 generation fpga user guide http://www.xilinx.com/ support/documentation / user _ guides/ug331.pdf ? clocking resources ? digital clock managers (dcms) ? block ram ? configurable logic blocks (clbs) - distributed ram - srl16 shift registers - carry and arithmetic logic ? i/o resources ? embedded multiplier blocks ? programmable interconnect ? ise? design tools ? ip cores ? embedded processing and control solutions ? pin types and package overview ? package drawings ? powering fpgas ? power management ? ug332: spartan-3 generation configuration user guide http://www.xilinx.com/su pport/documentation/ user_guides/ug332.pdf ? configuration overview - configuration pins and behavior - bitstream sizes ? detailed descriptions by mode - master serial mode using xilinx? platform flash prom - master spi mode using commodity spi serial flash prom - master bpi mode using commodity parallel nor flash prom - slave parallel (selectmap) using a processor - slave serial using a processor - jtag mode ? ise impact programming examples ? multiboot reconfiguration for specific hardware examples, please see the spartan-3e starter kit board web page, which has links to various design examples and the user guide. ? spartan-3e starter kit board page http://www.xilinx.com/s3estarter ? ug230: spartan-3e starter kit user guide http://www.xilinx.com/ support/documentation / userguides/ug230.pdf create a xilinx mysupport user account and sign up to receive automatic e-mail notification whenever this data sheet or the associated user guides are updated. ? sign up for alerts on xilinx mysupport http://www.xilinx.com/support/answers/19380.htm 116 spartan-3e fpga family: functional description DS312-2 (v3.8) august 26, 2009 0 product specification r functional description 10 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r introduction as described in architectural overview , the spartan?-3e fpga architecture consists of five fundamental functional elements: ? input/output blocks (iobs) ? configurable logic block (clb) and slice resources ? block ram ? dedicated multipliers ? digital clock managers (dcms) the following sections provide detailed information on each of these functions. in addition, this section also describes the following functions: ? clocking infrastructure ? interconnect ? configuration ? powering spartan-3e fpgas input/output blocks (iobs) for additional informat ion, refer to the ? using i/o resources ? chapter in ug331 . iob overview the input/output block (iob) provides a programmable, unidirectional or bidirectional interface between a package pin and the fpga?s internal logic. the iob is similar to that of the spartan-3 family with the following differences: ? input-only blocks are added ? programmable input delays are added to all blocks ? ddr flip-flops can be shared between adjacent iobs the unidirectional input-only block has a subset of the full iob capabilities. thus there ar e no connections or logic for an output path. the following paragraphs assume that any reference to output functionality does not apply to the input-only blocks. the number of input-only blocks varies with device size, but is never more than 25% of the total iob count. figure 5, page 11 is a simplified diagram of the iob?s inter- nal structure. there are three main signal paths within the iob: the output path, input path, and 3-state path. each path has its own pair of storage elements that can act as either registers or latches. for more information, see stor- age element functions . the three main signal paths are as follows: ? the input path carries data from the pad, which is bonded to a package pin, through an optional programmable delay element directly to the i line. after the delay element, there are alternate routes through a pair of storage elements to the iq1 and iq2 lines. the iob outputs i, iq1, and iq2 lead to the fpga?s internal logic. the delay element can be set to ensure a hold time of zero (see input delay functions ). ? the output path, starting with the o1 and o2 lines, carries data from the fpga?s internal logic through a multiplexer and then a three-state driver to the iob pad. in addition to this direct path, the multiplexer provides the option to insert a pair of storage elements. ? the 3-state path determines when the output driver is high impedance. the t1 and t2 lines carry data from the fpga?s internal logic through a multiplexer to the output driver. in addition to this direct path, the multiplexer provides the option to insert a pair of storage elements. ? all signal paths entering the iob, including those associated with the storage elements, have an inverter option. any inverter placed on these paths is automatically absorbed into the iob. functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 11 product specification r figure 5: simplified iob diagram tff1 three- s t a te p a th t t1 tce t2 tff2 q s r ddr mux rev q s r rev off1 o u tp u t p a th o1 oce o2 off2 q s r ddr mux keeper l a tch v cco v ref pin i/o pin from adj a cent iob d s3 12-2_19_110606 i/o pin progr a m- m ab le o u tp u t driver e s d p u ll-up p u ll- down e s d rev q s r rev otclk1 otclk2 iff1 inp u t p a th iddrin1 i ice iff2 q s r progr a mm ab le del a y lv c m o s , lvttl, pci s ingle-ended s t a nd a rd s us ing v ref differenti a l s t a nd a rd s rev d ce ck d ce ck d ce ck d ce ck d ce ck d ce ck q s r rev iddrin2 iclk1 iclk2 s r rev iq1 iq2 progr a mm ab le del a y notes: 1. all iob control and output path signals have an inverting polarity option wihtin the iob. 2. iddrin1/iddrin2 signals shown with dashed lines connect to the adjacent iob in a differ ential pair only, no t to the fpga fabr ic. functional description 12 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r input delay functions each iob has a programmable delay block that optionally delays the input signal. in figure 6 , the signal path has a coarse delay element that can be bypassed. the input sig- nal then feeds a 6-tap delay line. the coarse and tap delays vary; refer to timing reports for specific delay values. all six taps are available via a multiplexer for use as an asynchro- nous input directly into the fp ga fabric. in this way, the delay is programmable in 12 steps. three of the six taps are also available via a multiplexer to the d inputs of the syn- chronous storage elements. the delay inserted in the path to the storage element can be varied in six steps. the first, coarse delay element is common to both asynchronous and synchronous paths, and must be either used or not used for both paths. the delay values are set up in the silicon once at configura- tion time?they are non-modifiable in device operation. the primary use for the input delay element is to adjust the input delay path to ensure that there is no hold time require- ment when using the input flip-flop(s) with a global clock. the default value is chosen au tomatically by the xilinx soft- ware tools as the value depends on device size and the spe- cific device edge where the flip-flop resides. the value set by the xilinx ise software is indicated in the map report generated by the implementation tools, and the resulting effects on input timing are reported using the timing ana- lyzer tool. if the design uses a dcm in the clock path, then the delay element can be safely set to zero because the delay-locked loop (dll) compensation automatically ensures that there is still no input hold time requirement. both asynchronous and synchronous values can be modi- fied, which is useful where ex tra delay is required on clock or data inputs, for example, in interfaces to various types of ram. these delay values are defined through the ibuf_delay_value and the ifd_delay_value param- eters. the default ibuf_delay_value is 0, bypassing the delay elements for the asynchronous input. the user can set this parameter to 0-12. the default ifd_delay_value is auto. ibuf_delay_value and ifd_delay_value are independent for each input. if the same input pin uses both registered and non-registered input paths, both param- eters can be used, but they must both be in the same half of the total delay (both either bypassing or using the coarse delay element). figure 6: programmable fixed input delay elements pa d asynchrono u s inp u t (i) synchrono u s inp u t (iq2) synchrono u s inp u t (iq1) dq dq ug331_c10_09_01150 8 coarse delay ibuf_delay_ v alue ifd_delay_ v alue functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 13 product specification r storage element functions there are three pairs of storage elements in each iob, one pair for each of the three paths. it is possible to configure each of these storage elements as an edge-triggered d-type flip-flop (fd) or a level-sensitive latch (ld). the storage-element pair on either the output path or the three-state path can be used together with a special multi- plexer to produce double-data-rate (ddr) transmission. this is accomplished by taking data synchronized to the clock signal?s rising edge and converting it to bits syn- chronized on both the rising and the falling edge. the com- bination of two registers and a multiplexer is referred to as a double-data-rate d-type flip-flop (oddr2). ta b l e 4 describes the signal paths associated with the stor- age element. as shown in figure 5 , the upper registers in both the output and three-state paths share a common clock. the otclk1 clock signal drives the ck clock inputs of the upper registers on the output and three-state paths. similarly, otclk2 drives the ck inputs for the lower registers on the output and three-state paths. the upper and lower registers on the input path have independent clock lines: iclk1 and iclk2. the oce enable line controls the ce inputs of the upper and lower registers on the output path. similarly, tce con- trols the ce inputs for the register pair on the three-state path and ice does the same for the register pair on the input path. the set/reset (sr) line enteri ng the iob controls all six registers, as is the reverse (rev) line. in addition to the signal polarity controls described in iob overview , each storage element additionally supports the controls de scribed in ta bl e 5 . ta bl e 4 : storage element signal description storage element signal description function d data input data at this input is stored on the active edge of ck and enabled by ce. for latch operation when the input is enabled, data passes directly to the output q. q data output the data on this output reflects the state of the storage element. for operation as a latch in transparent mode, q mirrors the data at d. ck clock input data is loaded into the storage element on this input?s active edge with ce asserted. ce clock enable input when asserted, this input enables ck. if not connected, ce defaults to the asserted state. sr set/reset input this input forces the storage element into the state specified by the srhigh/srlow attributes. the sync/async attribute sett ing determines if the sr input is synchronized to the clock or not. if both sr and rev are active at the same time, the storage element gets a value of 0. rev reverse input this input is used together with sr. it forces the storage element into the state opposite from what sr does. the sync/async attribute setting determines whether the rev input is synchronized to the clock or not. if both sr and rev are active at the same time, the storage element gets a value of 0. ta bl e 5 : storage element options option switch function specificity ff/latch chooses between an edge-triggered flip-flop or a level-sensitive latch independent for each storage element sync/async determines whether the sr set/reset control is synchronous or asynchronous independent for each storage element functional description 14 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r double-data-rate transmission double-data-rate (ddr) transmission describes the tech- nique of synchronizing signals to both the rising and falling edges of the clock signal. spartan-3e devices use register pairs in all three iob path s to perform ddr operations. the pair of storage elements on the iob?s output path (off1 and off2), used as registers, combine with a spe- cial multiplexer to form a ddr d-type flip-flop (oddr2). this primitive permits ddr tr ansmission where output data bits are synchronized to both the rising and falling edges of a clock. ddr operation requires two clock signals (usually 50% duty cycle), one the inverted form of the other. these signals trigger the two registers in alternating fashion, as shown in figure 7 . the digital clock manager (dcm) gen- erates the two clock signals by mirroring an incoming signal, and then shifting it 180 degrees. this approach ensures minimal skew between the two signals. alternatively, the inverter inside the iob can be used to invert the clock sig- nal, thus only using one cloc k line and both rising and falling edges of that clock line as the two clocks for the ddr flip-flops. the storage-element pair on the three-state path (tff1 and tff2) also can be combined with a local multiplexer to form a ddr primitive. this permits synchronizing the output enable to both the rising an d falling edges of a clock. this ddr operation is realized in the same way as for the output path. the storage-element pair on the input path (iff1 and iff2) allows an i/o to receive a ddr signal. an incoming ddr clock signal triggers one register, and the inverted clock sig- nal triggers the other register. the registers take turns cap- turing bits of the incoming d dr data signal. the primitive to allow this functionality is called iddr2. aside from high bandwidth data transfers, ddr outputs also can be used to reproduce, or mirror , a clock signal on the output. this approach is used to transmit clock and data sig- nals together (source synchronously). a similar approach is used to reproduce a clock signal at multiple outputs. the advantage for both approaches is that skew across the out- puts is minimal. srhigh/srlow determines whether sr acts as a set, which forces the storage element to a logic "1" (srhigh) or a reset, which forces a logic "0" (srlow) independent for each storage element, except when using oddr2. in the latter case, the selection for the upper element will apply to both elements. init1/init0 when global set/reset (gsr) is asserted or after configuration this option specifies the initial state of the storage element, either set (init1) or reset (init0). by default, choosing srlow also selects init0; choosing srhigh also selects init1. independent for each storage element, except when using oddr2, which uses two iobs. in the oddr2 case, selecting init0 for one iobs applies to both elements within the iob, although init1 could be selected for the elements in the other iob. ta bl e 5 : storage element options (continued) option switch function specificity figure 7: two methods for clocking the ddr register DS312-2_20_021105 d1 clk1 ddr mux dcm q1 fddr d2 clk2 q2 1 8 0? 0? q d1 clk1 ddr mux dcm q1 fddr d2 clk2 q2 0? q functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 15 product specification r register cascade feature in the spartan-3e family, one of the iobs in a differential pair can cascade its input storage elements with those in the other iob as part of a differential pair. this is intended to make ddr operation at high speed much simpler to imple- ment. the new ddr connections that are available are shown in figure 5 (dashed lines), and are only available for routing between iobs and are not accessible to the fpga fabric. note that this feature is only available when using the differential i/o standards lvds, rsds, and mini_lvds. iddr2 as a ddr input pair, the master iob registers incoming data on the rising edge of iclk1 (= d1) and the rising edge of iclk2 (= d2), which is typically the same as the falling edge of iclk1. this data is then transferred into the fpga fabric. at some point, both signals must be brought into the same clock domain, typically iclk1. this can be difficult at high frequencies because the available time is only one half of a clock cycle assuming a 50% duty cycle. see figure 8 for a graphical illustration of this function. in the spartan-3e device, the signal d2 can be cascaded into the storage element of the adjacent slave iob. there it is re-registered to iclk1, and only then fed to the fpga fabric where it is now already in the same time domain as d1. here, the fpga fabric uses only the clock iclk1 to pro- cess the received data. see figure 9 for a graphical illustra- tion of this function. oddr2 as a ddr output pair, the master iob registers data coming from the fpga fabric on the rising edge of oclk1 (= d1) and the rising edge of oclk2 (= d2), which is typically the same as the falling edge of oclk1. these two bits of data are multiplexed by the ddr mux and forwarded to the out- put pin. the d2 data signal must be re-synchronized from the oclk1 clock domain to the oclk2 domain using fpga slice flip-flops. placement is critical at high frequencies, because the time available is only one half a clock cycle. see figure 10 for a graphical illustration of this function. the c0 or c1 alignment feature of the oddr2 flip-flop, orig- inally introduced in the spartan-3e fpga family, is not rec- ommended or supported in the ise development software. the oddr2 flip-flop without the alignment feature remains fully supported. without the alignment feature, the oddr2 feature behaves equivalent to the oddr flip-flop on previ- ous xilinx fpga families. figure 8: input ddr (without cascade feature) iclk2 to fa b ric pad d1 d2 d pad iclk1 d1 d2 d d+2 d+4 d+6 d+ 8 d+ 8 d+7 d+6 d+5 d+4 d+3 d+2 d+1 d-1 d+1 d+3 d+5 d+7 d q iclk1 iclk2 DS312-2_21_021105 d q figure 9: input ddr using spartan-3e cascade feature d q iclk1 to fabric pad d1 d2 pad iclk2 d q iclk1 iclk2 d q iq2 iddrin2 d1 d2 d-1 d+1 d+3 d+5 d+7 d d+2 d+4 d+6 d+8 d d+8 d+7 d+6 d+5 d+4 d+3 d+2 d+1 DS312-2_22_030105 functional description 16 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r selectio signal standards the spartan-3e i/os feature inputs and outputs that sup- port a wide range of i/o signaling standards ( ta bl e 6 and ta b l e 7 ). the majority of the i/os also can be used to form differential pairs to support any of the differential signaling standards ( ta bl e 7 ). to define the i/o signaling standard in a design, set the iostandard attribute to the appropriate setting. xilinx provides a variety of different methods for applying the iostandard for maximum flexibility. for a full description of different methods of applying attributes to control iostandard, refer to the xilinx software manuals and help. spartan-3e fpgas provide add itional input flexibility by allowing i/o standards to be mixed in different banks. for a particular v cco voltage, ta bl e 6 and ta bl e 7 list all of the iostandards that can be combined and if the iostan- dard is supported as an input only or can be used for both inputs and outputs. figure 10: output ddr d q oclk1 from fabric pad d2 d1 d+4 d+3 d+2 d+1 d pad oclk1 d1 d2 oclk2 d q oclk2 DS312-2_23_030105 d+1 d+3 d+5 d+7 d d+2 d+4 d+6 d+8 d+9 d+8 d+10 d+5 d+6 d+7 ta bl e 6 : single-ended iostandar d bank compatibility single-ended iostandard v cco supply/compatibility input requirements 1.2v 1.5v 1.8v 2.5v 3.3v v ref board termination voltag e (v tt ) lv t t l - - - - input/ output n/r (1) n/r lv c m o s 3 3 - - - - input/ output n/r n/r lv c m o s 2 5 - - - input/ output input n/r n/r lv c m o s 1 8 - - input/ output input input n/r n/r lv c m o s 1 5 - input/ output input input input n/r n/r lv c m o s 1 2 input/ output input input input input n/r (1) n/r pci33_3 - - - - input/ output n/r n/r pci66_3 - - - - input/ output n/r n/r hstl_i_18 - - input/ output input input 0.9 0.9 hstl_iii_18 - - input/ output input input 1.1 1.8 functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 17 product specification r hstl and sstl inputs use the reference voltage (v ref ) to bias the input-switching threshold. once a configuration data file is loaded into the fp ga that calls for the i/os of a given bank to use hstl/sstl, a few specifically reserved i/o pins on the same bank automatically convert to v ref inputs. for banks that do not contain hstl or sstl, v ref pins remain available for user i/os or input pins. differential standards employ a pair of signals, one the opposite polarity of the other. the noise canceling proper- ties (for example, common-mode rejection) of these stan- dards permit exceptionally high data transfer rates. this subsection introduces the diff erential signaling capabilities of spartan-3e devices. each device-package combination designates specific i/o pairs specially optimized to support differential standards. a unique l-number , part of the pin name, identifies the line-pairs associated with each bank (see pinout descrip- tions in module 4). for each pair, the letters p and n desig- nate the true and inverted lines, respectively. for example, the pin names io_l43p_3 and io_l43n_3 indicate the true and inverted lines comprising the line pair l43 on bank 3. sstl18_i - - input/ output input input 0.9 0.9 sstl2_i - - - input/ output input 1.25 1.25 notes: 1. n/r - not required for input operation. ta bl e 6 : single-ended iostandar d bank compatibility (continued) single-ended iostandard v cco supply/compatibility input requirements 1.2v 1.5v 1.8v 2.5v 3.3v v ref board termination voltag e (v tt ) ta bl e 7 : differential iostandard bank compatibility differential iostandard v cco supply input requirements: v ref differential bank restriction (1) 1.8v 2.5v 3.3v lvds_25 input input, on-chip differential termination, output input v ref is not used for these i/o standards applies to outputs only rsds_25 input input, on-chip differential termination, output input applies to outputs only mini_lvds_25 input input, on-chip differential termination, output input applies to outputs only lvpecl_25 input input input no differential bank restriction (other i/o bank restrictions might apply) blvds_25 input input, output input diff_hstl_i_18 input, output input input diff_hstl_iii_18 input, output input input diff_sstl18_i input, output input input diff_sstl2_i input input, output input notes: 1. each bank can support any two of the following: lvds_25 outputs, mini_lvds_25 outputs, rsds_25 outputs. functional description 18 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r v cco provides current to the outputs and additionally pow- ers the on-chip differential termination. v cco must be 2.5v when using the on-chip dif ferential termination. the v ref lines are not required for differential operation. to further understand how to combine multiple iostan- dards within a bank, refer to iobs organized into banks , page 19 . on-chip differential termination spartan-3e devices provide an on-chip ~120 differential termination across the input differential receiver terminals. the on-chip input differential termination in spartan-3e devices potentially eliminates the external 100 termination resistor commonly found in diff erential receiver circuits. dif- ferential termination is used for lvds, mini-lvds, and rsds as applications permit. on-chip differential terminatio n is available in banks with v cco = 2.5v and is not supported on dedicated input pins. set the diff_term attribute to true to enable differential termination on a differential i/o pin pair. the diff_term attribute uses the following syntax in the ucf file: inst diff_term = ? functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 19 product specification r high output current drive strength and fast output slew rates generally result in fastest i/o performance. however, these same settings generally also result in transmission line effects on the printed circuit board (pcb) for all but the shortest board traces. each iob has independent slew rate and drive strength controls. use the slowest slew rate and lowest output drive current that meets the performance requirements for the end application. likewise, due to lead inductance, a given package supports a limited number of simultaneous switching outputs (ssos) when using fast, high-drive outputs. only use fast, high-drive outputs when required by the application. iobs organized into banks the spartan-3e architecture organizes iobs into four i/o banks as shown in figure 13 . each bank maintains sepa- rate v cco and v ref supplies. the separate supplies allow each bank to independently set v cco . similarly, the v ref supplies can be set for each bank. refer to ta bl e 6 and ta bl e 7 for v cco and v ref requirements. when working with spartan-3e devices, most of the differ- ential i/o standards are compatible and can be combined within any given bank. each bank can support any two of the following differential standards: lvds_25 outputs, mini_lvds_25 outputs, and rsds_25 outputs. as an example, lvds_25 outputs, rsds_25 outputs, and any other differential inputs while using on-chip differential ter- mination are a valid combination. a combination not allowed is a single bank with lvds_25 outputs, rsds_25 outputs, and mini_lvds_25 outputs. i/o banking rules when assigning i/os to banks, these v cco rules must be followed: 1. all v cco pins on the fpga must be connected even if a bank is unused. 2. all v cco lines associated within a bank must be set to the same voltage level. 3. the v cco levels used by all standards assigned to the i/os of any given bank must agree. the xilinx development software checks for this. ta b l e 6 and ta b l e 7 describe how different standards use the v cco supply. 4. if a bank does not have any v cco requirements, connect v cco to an available voltage, such as 2.5v or 3.3v. some configuration modes might place additional v cco requirements. refer to configuration for more information. if any of the standards assigned to the inputs of the bank use v ref , then the following additional rules must be observed: 1. all v ref pins must be connected within a bank. 2. all v ref lines associated with the bank must be set to the same voltage level. 3. the v ref levels used by all standards assigned to the inputs of the bank must ag ree. the xilinx development software checks for this. ta b l e 6 describes how different standards use the v ref supply. if v ref is not required to bias th e input switching thresholds, all associated v ref pins within the bank can be used as user i/os or input pins. package footprint compatibility sometimes, applications outgrow the logic capacity of a specific spartan-3e fpga. fortunately, the spartan-3e family is designed so that mult iple part types are available in pin-compatible package footprints, as described in pinout descriptions in module 4. in some cases, there are subtle differences between devices available in the same footprint. these differences are outlined for each package, such as pins that are unconnected on one device but connected on another in the same package or pins that are dedicated inputs on one package but full i/o on another. when design- ing the printed circuit board (pcb), plan for potential future upgrades and package migration. the spartan-3e family is not pin-compatible with any previ- ous xilinx fpga family. dedicated inputs dedicated inputs are iobs used only as inputs. pin names designate a dedicated input if the name starts with ip , for example, ip or ip_lxxx_x. dedicated inputs retain the full functionality of the iob for input functions with a single lvcmos25 - lvcmos18 - - lvcmos15 - - - lvcmos12 - - - - - figure 13: spartan-3e i/o banks (top view) ta bl e 8 : programmable output drive current iostandard output drive current (ma) 2 4 6 8 12 16 DS312-2_26_021205 bank 0 bank 2 bank 3 bank 1 functional description 20 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r exception for differential inputs (ip_lxxx_x). for the differ- ential dedicated inputs, the on-chip differential termination is not available. to replace the on-chip differential termina- tion, choose a differential pair that supports outputs (io_lxxx_x) or use an external 100 termination resistor on the board. esd protection clamp diodes protect all device pads against damage from electro-static discharge (esd) as well as excessive voltage transients. each i/o has two clamp diodes: one diode extends p-to-n from the pad to v cco and a second diode extends n-to-p from the pad to gnd. during operation, these diodes are normally biased in the off state. these clamp diodes are always connected to the pad, regardless of the signal standard selected. the presence of diodes lim- its the ability of spartan-3e i/os to tolerate high signal volt- ages. the v in absolute maximum rating in ta bl e 7 3 of dc and switching characteristics (module 3) specifies the voltage range that i/os can tolerate. supply voltages for the iobs the iobs are powered by three supplies: 1. the v cco supplies, one for each of the fpga?s i/o banks, power the output drivers. the voltage on the v cco pins determines the voltage swing of the output signal. 2. v ccint is the main power supply for the fpga?s internal logic. 3. v ccaux is an auxiliary source of power, primarily to optimize the performance of various fpga functions such as i/o switching. i/o and input-only pin behavior during power-on, configurat ion, and user mode in this section, all behavior described for i/o pins also applies to input-only pins and dual-purpose i/o pins that are not actively involved in the cu rrently-selected configuration mode. all i/o pins have esd clamp diodes to their respective v cco supply and from gnd, as shown in figure 5 . the v ccint (1.2v), v ccaux (2.5v), and v cco supplies can be applied in any order. before the fpga can start its configuration pro- cess, v ccint , v cco bank 2, and v ccaux must have reached their respective minimum recommended operating levels indicated in ta b l e 7 4 . at this time, all output drivers are in a high-impedance state. v cco bank 2, v ccint , and v ccaux serve as inputs to the internal power-on reset circuit (por). a low level applied to the hswap input enables pull-up resistors on user-i/o and input-only pins from power-on throughout configuration. a high level on hswap disables the pull-up resistors, allowing the i/os to float. hswap con- tains an internal pull-up resistor and defaults to high if left floating. as soon as power is applied, the fpga begins ini- tializing its configuration me mory. at the same time, the fpga internally asserts the gl obal set-reset (gsr), which asynchronously resets all iob storage elements to a default low state. also see pin behavior during configuration . upon the completion of initialization and the beginning of configuration, init_b goes high, sampling the m0, m1, and m2 inputs to determine the configuration mode. configura- tion data is then loaded into the fpga. the i/o drivers remain in a high-impedance state (with or without pull-up resistors, as determined by the hswap input) throughout configuration. at the end of configuration, the gsr net is released, placing the iob registers in a low state by default, unless the loaded design reverses the polarity of their respective sr inputs. the global three state (gts) net is released during start-up, marking the end of configuration and the begin- ning of design operation in the user mode. after the gts net is released, all user i/os go active while all unused i/os are pulled down (pulldown). the designer can control how the unused i/os are terminated after gts is released by setting the bitstream generator (bitgen) option unused- pin to pullup, pulldown, or float. one clock cycle later (default), the global write enable (gwe) net is released allowing the ram and registers to change states. once in user mode, any pull-up resistors enabled by hswap revert to the user settings and hswap is available as a general-purpose i/o. for more information on pullup and pulldown, see pull-up and pull-down resistors . behavior of unused i/o pins after configuration by default, the xilinx ise de velopment software automati- cally configures all unused i/o pins as input pins with indi- vidual internal pull-down resistors to gnd. this default behavior is controlled by the unusedpin bit- stream generator (bitgen) option, as described in ta b l e 6 9 . jtag boundary-scan capability all spartan-3e iobs support boundary-scan testing com- patible with ieee 1149.1/1532 standards. during bound- ary-scan operations such as extest and highz the pull-down resistor is active. see jtag mode for more infor- mation on programming via jtag. functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 21 product specification r configurable logic block (clb) and slice resources for additional information, refer to the ? using configurable logic blocks (clbs) ? chapter in ug331 . clb overview the configurable logic blocks (clbs) constitute the main logic resource for implementing synchronous as well as combinatorial circuits. each cl b contains four slices, and each slice contains two look-up tables (luts) to imple- ment logic and two dedicated storage elements that can be used as flip-flops or latches. the luts can be used as a 16x1 memory (ram16) or as a 16-bit shift register (srl16), and additional multiplexers and carry logic simplify wide logic and arithmetic functions. most general-purpose logic in a design is automatically mapped to the slice resources in the clbs. each clb is identical, and the spartan-3e family clb structure is identical to that for the spartan-3 family. clb array the clbs are arranged in a regular array of rows and col- umns as shown in figure 14 . each density varies by the number of rows and columns of clbs (see ta b l e 9 ). slices each clb comprises four interconnected slices, as shown in figure 16 . these slices are grouped in pairs. each pair is organized as a column with an independent carry chain. the left pair supports both logic and memory functions and its slices are called slicem. the right pair supports logic only and its slices are called slicel. therefore half the luts support both logic and memory (including both ram16 and srl16 shift registers) while half support logic only, and the two types alternate throughout the array col- umns. the slicel reduces the size of the clb and lowers the cost of the device, and can also provide a performance advantage over the slicem. figure 14: clb locations DS312-2_31_021205 spartan-3e fpga x0y1 x1y1 x0y0 x1y0 iobs clb slice x2y1 x3y1 x2y0 x3y0 x0y3 x1y3 x0y2 x1y2 x2y3 x3y3 x2y2 x3y2 ta bl e 9 : spartan-3e clb resources device clb rows clb columns clb total (1) slices luts / flip-flops equivalent logic cells ram16 / srl16 distributed ram bits xc3s100e 22 16 240 960 1,920 2,160 960 15,360 xc3s250e 34 26 612 2,448 4,896 5,508 2,448 39,168 xc3s500e 46 34 1,164 4,656 9,312 10,476 4,656 74,496 xc3s1200e 60 46 2,168 8,672 17,344 19,512 8,672 138,752 xc3s1600e 76 58 3,688 14,752 29,504 33,192 14,752 236,032 notes: 1. the number of clbs is less than the multiple of the rows and columns because the block ram/multiplier blocks and the dcms are embedded in the array (see figure 1 in module 1). functional description 22 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r . figure 15: simplified diagram of the left-hand slicem wf[4:1] DS312-2_32_042007 d di di ws notes: 1. options to invert signal polarity as well as other options that enable lines for various functions are not shown. 2. the index i can be 6, 7, or 8, depending on the slice. the upper slicel has an f8mux, and the upper slicem has an f7mux. the lower slicel and slicem both have an f6mux. functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 23 product specification r slice location designations the xilinx development software designates the location of a slice according to its x and y coordinates, starting in the bottom left corner, as shown in figure 14 . the letter ?x? fol- lowed by a number identifies columns of slices, increment- ing from the left side of the die to the right. the letter ?y? followed by a number identifies the position of each slice in a pair as well as indicating the clb row, incrementing from the bottom of the die. figure 16 shows the clb located in the lower left-hand corner of the die. the slicem always has an even ?x? number, and the slicel always has an odd ?x? number. slice overview a slice includes two lut function generators and two stor- age elements, along with additional logic, as shown in figure 17 . both slicem and slicel have the following elements in common to provide logic, arithmetic, and rom functions: ? two 4-input lut function generators, f and g ? two storage elements ? two wide-function multiplexers, f5mux and fimux ? carry and arithmetic logic figure 16: arrangement of slices within the clb ds099-2_05_0 8 2104 interconnect to neigh b ors left-hand slicem (logic or distri bu ted ram or shift register) right-hand slicel (logic only) cin slice x0y1 slice x0y0 switch matrix cout clb cout shiftout shiftin cin slice x1y1 slice x1y0 figure 17: resources in a slice fimux f5mux register carry carry register arithmetic logic slicem slicel srl16 ram16 lut4 (g) srl16 ram16 lut4 (f) fimux f5mux register carry carry register arithmetic logic lut4 (g) lut4 (f) DS312-2_13_020905 functional description 24 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r the slicem pair supports two additional functions: ? two 16x1 distributed ram blocks, ram16 ? two 16-bit shift registers, srl16 each of these elements is described in more detail in the fol- lowing sections. logic cells the combination of a lut and a storage element is known as a ?logic cell?. the additional features in a slice, such as the wide multiplexers, carry logic, and arithmetic gates, add to the capacity of a slice, implementing logic that would oth- erwise require additional luts. benchmarks have shown that the overall slice is equivale nt to 2.25 simple logic cells. this calculation provides the equivalent logic cell count shown in ta b l e 9 . slice details figure 15 is a detailed diagram of the slicem. it represents a superset of the elements and connections to be found in all slices. the dashed and gray lines (blue when viewed in color) indicate the resources found only in the slicem and not in the slicel. each slice has two halves, which are differentiated as top and bottom to keep them distinct from the upper and lower slices in a clb. the control inputs for the clock (clk), clock enable (ce), slice write enable (slicewe1), and reset/set (rs) are shared in common between the two halves. the luts located in the top and bottom portions of the slice are referred to as "g" and "f", respectively, or the "g-lut" and the "f-lut". the storage elements in the top and bot- tom portions of the slice are called ffy and ffx, respec- tively. each slice has two multiplexe rs with f5mux in the bottom portion of the slice and fimux in the top portion. depending on the slice, the fimux takes on the name f6mux, f7mux, or f8mux, according to its position in the multi- plexer chain. the lower slicel and slicem both have an f6mux. the upper slicem has an f7mux, and the upper slicel has an f8mux. the carry chain enters the bottom of the slice as cin and exits at the top as cout. five multiplexers control the chain: cyinit, cy0f, and cymuxf in the bottom portion and cy0g and cymuxg in the top portion. the dedicated arith- metic logic includes the exclusive-or gates xorf and xorg (bottom and top portions of the slice, respectively) as well as the and gates fand and gand (bottom and top portions, respectively). see ta b l e 1 0 for a description of all the slice input and out- put signals. ta bl e 1 0 : slice inputs and outputs name location direction description f[4:1] slicel/m bottom input f-lut and fand inputs g[4:1] slicel/m top input g-lut and gand inputs or write address (slicem) bx slicel/m bottom input bypass to or output (slicem) or storage element, or control input to f5mux, input to carry logic, or data input to ram (slicem) by slicel/m top input bypass to or output (slicem) or storage element, or control input to fimux, input to carry logic, or data input to ram (slicem) bxout slicem bottom output bx bypass output byout slicem top output by bypass output altdig slicem top input alternate data input to ram dig slicem top output altdig or shiftin bypass output slicewe1 slicem common input ram write enable f5 slicel/m bottom output output from f5mux; direct feedback to fimux fxina slicel/m top input input to fimux; direct feedback from f5mux or another fimux fxinb slicel/m top input input to fimux; direct feedback from f5mux or another fimux fi slicel/m top output output from fimux; direct feedback to another fimux ce slicel/m common input ffx/y clock enable sr slicel/m common input ffx/y set or reset or ram write enable (slicem) functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 25 product specification r main logic paths central to the operation of each slice are two nearly identi- cal data paths at the top and bottom of the slice. the description that follows uses names associated with the bot- tom path. (the top path names appear in parentheses.) the basic path originates at an interconnect switch matrix out- side the clb. see interconnect for more information on the switch matrix and the routing connections. four lines, f1 through f4 (or g1 through g4 on the upper path), enter the slice and connect directly to the lut. once inside the slice, the lower 4-bit path passes through a lut ?f? (or ?g?) that performs logi c operations. the lut data out- put, ?d?, offers five possible paths: 1. exit the slice via line "x" (or "y") and return to interconnect. 2. inside the slice, "x" (or "y") serves as an input to the dxmux (or dymux) which feeds the data input, "d", of the ffx (or ffy) storage element. the "q" output of the storage element drives the line xq (or yq) which exits the slice. 3. control the cymuxf (or cymuxg) multiplexer on the carry chain. 4. with the carry chain, serve as an input to the xorf (or xorg) exclusive-or gate that performs arithmetic operations, producing a result on "x" (or "y"). 5. drive the multiplexer f5mux to implement logic functions wider than four bits. the "d" outputs of both the f-lut and g-lut serve as data inputs to this multiplexer. in addition to the main logic paths described above, there are two bypass paths that enter the slice as bx and by. once inside the fpga, bx in the bottom half of the slice (or by in the top half) can take any of several possible branches: 1. bypass both the lut and the storage element, and then exit the slice as bxout (or byout) and return to interconnect. 2. bypass the lut, and then pass through a storage element via the d input before exiting as xq (or yq). 3. control the wide function multiplexer f5mux (or fimux). 4. via multiplexers, serve as an input to the carry chain. 5. drive the di input of the lut. 6. by can control the rev inputs of both the ffy and ffx storage elements. see storage element functions . 7. finally, the dig_mux multiplexer can switch by onto the dig line, which exits the slice. the control inputs clk, ce, sr, bx and by have program- mable polarity. the lut inputs do not need programmable polarity because their function can be inverted inside the lut. the sections that follow prov ide more detail on individual functions of the slice. look-up tables the look-up table or lut is a ram-based function gener- ator and is the main resource for implementing logic func- tions. furthermore, the luts in each slicem pair can be configured as distributed ram or a 16-bit shift register, as described later. each of the two luts (f and g) in a slice have four logic inputs (a1-a4) and a single output (d). any four-variable boolean logic operation can be implemented in one lut. functions with more inputs can be implemented by cascad- clk slicel/m common input ffx/y clock or ram clock (slicem) shiftin slicem top input data input to g-lut ram shiftout slicem bottom output shift data output from f-lut ram cin slicel/m bottom input carry chain input cout slicel/m top output carry chain output x slicel/m bottom output combinatorial output y slicel/m top output combinatorial output xb slicel/m bottom output combinatorial output from carry or f-lut srl16 (slicem) yb slicel/m top output combinatorial output from carry or g-lut srl16 (slicem) xq slicel/m bottom output ffx output yq slicel/m top output ffy output ta bl e 1 0 : slice inputs and outputs (continued) name location direction description functional description 26 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r ing luts or by using the wide function multiplexers that are described later. the output of the lut can connect to the wide multiplexer logic, the carry and arithmetic logic, or directly to a clb out- put or to the clb storage element. see figure 18 . wide multiplexers for additional information, refer to the ? using dedicated multiplexers ? chapter in ug331 . wide-function multiplexers effectively combine luts in order to permit more complex logic operations. each slice has two of these multiplexers with f5mux in the bottom por- tion of the slice and fimux in the top portion. the f5mux multiplexes the two luts in a slice. the fimux multiplexes two clb inputs which connect directly to the f5mux and fimux results from the same slice or from other slices. see figure 19 . depending on the slice, fimux takes on the name f6mux, f7mux, or f8mux. the designation indicates the number of inputs possible without restriction on the function. for example, an f7mux can generate any function of seven inputs. figure 20 shows the names of the multiplexers in each position in the spartan-3e clb. the figure also includes the direct connections within the clb, along with the f7mux connection to the clb below. each mux can create logic functions of more inputs than indicated by its name. the f5mux, for example, can gener- ate any function of five inputs, with four inputs duplicated to two luts and the fifth input controlling the mux. because each lut can implement independent 2:1 muxes, the f5mux can combine them to create a 4:1 mux, which is a six-input function. if the two luts have completely indepen- dent sets of inputs, some functions of all nine inputs can be implemented. ta bl e 1 1 shows the connections for each mul- tiplexer and the number of inputs possible for different types of functions. figure 18: lut resources in a slice a[4:1] f[4:1] 4 4 DS312-2_33_111105 f-lut g[4:1] d a[4:1] yq y g-lut ffy ffx d xq x figure 19: dedicated multiplexers in spartan-3e clb fimux fx (local feed b ack to fxin) y (general interconnect) yq 0 1 0 1 fxina fxinb f[4:1] g[4:1] dq f5mux by bx f5 (local feed b ack to fxin) x (general interconnect) xq dq lut lut x312-2_34_021205 functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 27 product specification r figure 20: muxes and dedicated feedback in spartan-3e clb DS312-2_3 8 _021305 f5 f 8 f5 f6 f5 f7 f5 f6 f5 fx f5 fx f5 x fxina fxinb fxina fxinb fxina fxinb fxina fxinb f5 fx ta bl e 1 1 : mux capabilities mux usage input source total number of inputs per function for any function for mux for limited functions f5mux f5mux luts 5 6 (4:1 mux) 9 fimux f6mux f5mux 6 11 (8:1 mux) 19 f7mux f6mux 7 20 (16:1 mux) 39 f8mux f7mux 8 37 (32:1 mux) 79 functional description 28 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r the wide multiplexers can be used by the automatic tools or instantiated in a design using a component such as the f5mux. the symbol, signals, and function are described below. the description is similar for the f6mux, f7mux, and f8mux. each has versions with a general output, local output, or both. carry and arithmetic logic for additional information, refer to the ? using carry and arithmetic logic ? chapter in ug331 . the carry chain, together with various dedicated arithmetic logic gates, support fast and efficient implementations of math operations. the carry logic is automatically used for most arithmetic functions in a design. the gates and multi- plexers of the carry and arithmetic logic can also be used for general-purpose logic, including simple wide boolean func- tions. the carry chain enters the slice as cin and exits as cout, controlled by several multiple xers. the carry chain connects directly from one clb to the clb above. the carry chain can be initialized at any point from the bx (or by) inputs. the dedicated arithmetic logic includes the exclusive-or gates xorf and xorg (upper and lower portions of the slice, respectively) as well as the and gates gand and fand (upper and lower portions, respectively). these gates work in conjunction with the luts to implement efficient arithmetic functions, including counters and multipliers, typ- ically at two bits per slice. see figure 22 and ta bl e 1 4 . figure 21: f5mux with local and general outputs ta bl e 1 2 : f5mux inputs and outputs signal function i0 input selected when s is low i1 input selected when s is high s select input lo local output that connects to the f5 or fx clb pins, which use local feedback to the fxin inputs to the fimux for cascading o general output that connects to the general-purpose combinatorial or registered outputs of the clb o i0 i1 0 1 s lo DS312-2_35_021205 table 13: f5mux function inputs outputs si0i1 o lo 01 x1 1 00 x0 0 1 x1 1 1 1 x0 0 0 functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 29 product specification r figure 22: carry logic ta bl e 1 4 : carry logic functions function description cyinit initializes carry chain for a slice. fixed selection of: ? cin carry input from the slice below ? bx input cy0f carry generation for bottom ha lf of slice. fixed selection of: ? f1 or f2 inputs to the lut (both equal 1 when a carry is to be generated) ? fand gate for multiplication ? bx input for carry initialization ? fixed "1" or "0" input for use as a simple boolean function cy0g carry generation for top half of slice. fixed selection of: ? g1 or g2 inputs to the lut (both equal 1 when a carry is to be generated) ? gand gate for multiplication ? by input for carry initialization ? fixed "1" or "0" input for use as a simple boolean function cymuxf carry generation or propagation mux for bott om half of slice. dynamic selection via cyself of: ? cyinit carry propagation (cyself = 1) ? cy0f carry generation (cyself = 0) cy0f cyself 1 xorf d a[4:1] f[4:1] 4 cymuxf cyinit xb xq x 0 1 cin DS312-2_14_021305 fand f1 f2 bx f-lut ffx g[4:1] cy0g cyselg 1 xorg d a[4:1] cymuxg yb cout yq y 0 1 gand g1 g2 by g-lut ffy functional description 30 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r the basic usage of the carry logic is to generate a half-sum in the lut via an xor function, which generates or propa- gates a carry out cout via the carry mux cymuxf (or cymuxg), and then complete the sum with the dedicated xorf (or xorg) gate and the carry input cin. this struc- ture allows two bits of an arit hmetic function in each slice. the cymuxf (or cymuxg) can be instantiated using the muxcy element, and the xorf (or xorg) can be instan- tiated using the xorcy element. the fand (or gand) gate is used for partial product multi- plication and can be instantiated using the mult_and component. partial products are generated by two-input and gates and then added. the carry logic is efficient for the adder, but one of the inputs must be outside the lut as shown in figure 23 . the fand (or gand) gate is used to duplicate one of the partial products, while the lut gener- ates both partial products and the xor function, as shown in figure 24 . cymuxg carry generation or propagation mux for top half of slice. dynamic selection via cyself of: ? cymuxf carry propagation (cyselg = 1) ? cy0g carry generation (cyselg = 0) cyself carry generation or propagation select for bottom half of slice. fixed selection of: ? f-lut output (typically xor result) ? fixed "1" to always propagate cyselg carry generation or propagation select for top half of slice. fixed selection of: ? g-lut output (typic ally xor result) ? fixed "1" to always propagate xorf sum generation for bottom half of slice. inputs from: ? f-lut ? cyinit carry signal from previous stage result is sent to either the combinatorial or registered output for the top of the slice. xorg sum generation for top half of slice. inputs from: ? g-lut ? cymuxf carry signal from previous stage result is sent to either the combinatorial or registered output for the top of the slice. fand multiplier partial product for bottom half of slice. inputs: ? f-lut f1 input ? f-lut f2 input result is sent through cy0f to become the carry generate signal into cymuxf gand multiplier partial product fo r top half of slice. inputs: ? g-lut g1 input ? g-lut g2 input result is sent through cy0g to become the carry generate signal into cymuxg ta bl e 1 4 : carry logic functions (continued) function description figure 23: using the muxcy and xorcy in the carry logic xorcy lut muxcy b a s u m cin DS312-2_37_021305 cout figure 24: using the mult_and for multiplication in carry logic b n+1 a m b n a m+1 p m+1 cin DS312-2_39_021305 cout lut mult_and functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 31 product specification r the mult_and is useful for sm all multipliers. larger multi- pliers can be built using th e dedicated 18x18 multiplier blocks (see dedicated multipliers ). storage elements the storage element, which is programmable as either a d-type flip-flop or a level-sensitive transparent latch, pro- vides a means for synchronizing data to a clock signal, among other uses. the storage elements in the top and bot- tom portions of the slice are called ffy and ffx, respec- tively. ffy has a fixed multiplexer on the d input selecting either the combinatorial output y or the bypass signal by. ffx selects between the combinatorial output x or the bypass signal bx. the functionality of a slice storage element is identical to that described earlier for the i/o storage elements. all sig- nals have programmable polarity; the default active-high function is described. the control inputs r, s, ce, and c are all shared between the two flip-flops in a slice. ta bl e 1 5 : storage element signals signal description d input. for a flip-flop data on the d input is loaded when r and s (or clr and pre) are low and ce is high during the low-to-high clock transition. for a latch, q reflects the d input while the gate (g) input and gate enable (ge) are high and r and s (or clr and pre) are low. the data on the d input during the high-to-low gate transition is stored in the latch. the data on the q output of the latch remains unchanged as long as g or ge remains low. q output. toggles after the low-to-high clock transition for a flip-flop and immediately for a latch. c clock for edge-triggered flip-flops. g gate for level-sensitive latches. ce clock enable for flip-flops. ge gate enable for latches. s synchronous set (q = high). when the s input is high and r is low, the flip-flop is set, output high, during the low-to-high clock (c) transition. a latch output is immediately set, output high. r synchronous reset (q = low); has precedence over set. pre asynchronous preset (q = high). when the pre input is high and clr is low, the f lip-flop is set, output high, during the low-to-high clock (c) transition. a la tch output is immediately set, output high. clr asynchronous clear (q = low); has precedence over preset to reset q output low sr clb input for r, s, clr, or pre rev clb input for opposite of sr. must be asynchronous or synchronous to match sr. figure 25: fd flip-flop component with synchronous reset, set, and clock enable fdrse dq ce c r s DS312-2_40_021305 table 16: fd flip-flop functionality with synchronous reset, set, and clock enable inputs outputs rscedc q 1 x x x 0 01 x x 1 000 x x no change 0011 1 0010 0 functional description 32 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r initialization the clb storage elements are initialized at power-up, dur- ing configuration, by the global gsr signal, and by the indi- vidual sr or rev inputs to the clb. the storage elements can also be re-initialized using the gsr input on the startup_spartan3e primitive. see global controls (startup_spartan3e) . distributed ram for additional information, refer to the ? using look-up tables as distributed ram ? chapter in ug331 . the luts in the slicem can be programmed as distributed ram. this type of memory affords moderate amounts of data buffering anywhere along a data path. one slicem lut stores 16 bits (ram16). the four lut inputs f[4:1] or g[4:1] become the address lines labeled a[4:1] in the device model and a[3:0] in the design components, provid- ing a 16x1 configuration in one lut. multiple slicem luts can be combined in various ways to store larger amounts of data, including 16x4, 32x2, or 64x1 configurations in one clb. the fifth and sixth address lines required for the 32-deep and 64-deep configurations, respectively, are implemented using the bx and by inputs, which connect to the write enable logic for writing and the f5mux and f6mux for reading. writing to distributed ram is always synchronous to the slicem clock (wclk for distributed ram) and enabled by the slicem sr input which functions as the active-high write enable (we). the read operation is asynchronous, and, therefore, during a write, the output initially reflects the old data at the address being written. the distributed ram outputs can be captured using the flip-flops within the slicem element. the we write-enable control for the ram and the ce clock-enable control for the flip-flop are independent, but the wclk and clk clock inputs are shared. because the ram read operation is asynchronous, the output data always reflects the currently addressed ram location. a dual-port option combines two luts so that memory access is possible from two independent data lines. the same data is written to both 16x1 memories but they have independent read address lines and outputs. the dual-port function is implemented by cascading the g-lut address lines, which are used for both read and write, to the f-lut write address lines (wf[4:1] in figure 15 ), and by cascad- ing the g-lut data input d1 through the dif_mux in figure 15 and to the d1 input on the f-lut. one clb pro- vides a 16x1 dual-port memory as shown in figure 26 . any write operation on the d input and any read operation on the spo output can occur simultaneously with and inde- pendently from a read operation on the second read-only port, dpo. ta bl e 1 7 : slice storage element initialization signal description sr set/reset input. forces the storage element into the state specified by the attribute srhigh or srlow. srhigh forces a logic ?1? when sr is asserted. srlow forces a logic ?0?. for each slice, set and reset can be set to be synchronous or asynchronous. rev reverse of set/reset input. a second input (by) forces the storage element into the opposite state. the reset condition is predominant over the set condition if both are active. same synchronous/asynchronous setting as for sr. gsr global set/reset. gsr defaults to active high but can be inverted by adding an inverter in front of the gsr input of the startup_spartan3e element. the initial state after configuration or gsr is defined by a separate init0 and init1 attribute. by default, setting the srlow attribute sets init0, and setting the srhigh attribute sets init1. functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 33 product specification r figure 26: ram16x1d dual-port usage d a[3:0] w e w clk spo dpo dpra[3:0] 16x1 lut ram (read/ w rite) 16x1 lut ram (read only) optional register optional register slicem DS312-2_41_021305 figure 27: dual-port ram component ta bl e 1 8 : dual-port ram function inputs outputs we (mode) wclk d spo dpo 0 (read) x x data_a data_d 1 (read) 0 x data_a data_d 1 (read) 1 x data_a data_d 1 (write) d d data_d 1 (read) x data_a data_d notes: 1. data_a = word addressed by bits a3-a0. 2. data_d = word addresse d by bits dpra3-dpra0. ram16x1d w e spo d w clk a0 a1 a2 a3 dpra0 dpra1 dpra2 dpra3 dpo DS312-2_42_021305 table 19: distributed ram signals signal description wclk the clock is used for synchronous writes. the data and the address input pins have setup times referenced to the wclk pin. active on the positive edge by default with built-in programmable polarity. we the enable pin affects the write functionality of the port. an inactive write enable prevents any writing to memory cells. an active write enable causes the clock edge to write the data input signal to the memory location pointed to by the address inputs. active high by default with built-in programmable polarity. a0, a1, a2, a3 (a4, a5) the address inputs select the memory cells for read or write. the width of the port determines the required address inputs. d the data input provides the new data value to be written into the ram. o, spo, and dpo the data output o on single-port ram or the spo and dpo outputs on dual-port ram reflects the contents of the memory cells referenced by the address inputs. following an active write clock edge, the data out (o or spo) reflects the newly written data. functional description 34 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r the init attribute can be used to preload the memory with data during fpga configuration. the default initial contents for ram is all zeros. if the we is held low, the element can be considered a rom. the rom function is possible even in the slicel. the global write enable signal, gwe, is asserted automati- cally at the end of device configuration to enable all writable elements. the gwe signal guarantees that the initialized distributed ram contents are not disturbed during the con- figuration process. the distributed ram is useful for smaller amounts of mem- ory. larger memory requirements can use the dedicated 18kbit ram blocks (see block ram ). shift registers for additional information, refer to the ? using look-up tables as shift registers (srl16) ? chapter in ug331 . it is possible to program each slicem lut as a 16-bit shift register (see figure 28 ). used in this way, each lut can delay serial data anywhere from 1 to 16 clock cycles without using any of the dedicated flip-flops. the resulting program- mable delays can be used to balance the timing of data pipelines. the slicem luts cascade from the g-lut to the f-lut through the difmux (see figure 15 ). shiftin and shiftout lines cascade a sl icem to the slicem below to form larger shift registers. the four slicem luts of a single clb can be combined to produce delays up to 64 clock cycles. it is also possible to combine shift registers across more than one clb. each shift register provides a shift output mc15 for the last bit in each lut, in addition to providing addressable access to any bit in the shift register through the normal d output. the address inputs a[3:0] are the same as the distributed ram address lines, which come from the lut inputs f[4:1] or g[4:1]. at the end of the shift register, the clb flip-flop can be used to provide one more shift delay for the addres- sable bit. the shift register element is known as the srl16 (shift register lut 16-bit), with a ?c? added to signify a cascade ability (q15 output) and ?e? to indicate a clock enable. see figure 29 for an example of the srlc16e component. i the functionality of the shift register is shown in ta b l e 2 0 . the srl16 shifts on the rising edge of the clock input when the clock enable control is hig h. this shift register cannot be initialized either during configuration or during operation except by shifting data into it. the clock enable and clock inputs are shared between the two luts in a slicem. the clock enable input is automatically kept active if unused. figure 28: logic cell srl16 structure a[3:0] shiftin shiftout or yb di (by) d mc15 di w sg ce (sr) clk srlc16 d q shift-reg w e ck a[3:0] o u tp u t registered o u tp u t (optional) 4 x465_03_040203 w s figure 29: srl16 shift register component with cascade and clock enable table 20: srl16 shift register function inputs outputs am clk ce d q q15 am x0 x q[am] q[15] am 1 d q[am-1] q[15] notes: 1. m = 0, 1, 2, 3. srlc16e dq ce clk a0 a1 a2 a3 q15 DS312-2_43_021305 functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 35 product specification r block ram for additional information, refer to the ? using block ram ? chapter in ug331 . spartan-3e devices incorporate 4 to 36 dedicated block rams, which are organized as dual-port configurable 18 kbit blocks. functionally, the block ram is identical to the spartan-3 architecture block ram. block ram synchro- nously stores large amounts of data while distributed ram, previously described, is better suited for buffering small amounts of data anywhere along signal paths. this section describes basic block ram functions. each block ram is configurable by setting the content?s ini- tial values, default signal value of the output registers, port aspect ratios, and write modes. block ram can be used in single-port or dual-port modes. arrangement of ram blocks on die the block rams are located together with the multipliers on the die in one or two columns depending on the size of the device. the xc3s100e has one column of block ram. the spartan-3e devices ranging from the xc3s250e to xc3s1600e have two columns of block ram. ta bl e 2 1 shows the number of ram blocks, the data storage capac- ity, and the number of columns for each device. row(s) of clbs are located above and below each block ram col- umn. immediately adjacent to each block ram is an embedded 18x18 hardware multiplier. the upper 16 bits of the block ram's port a data input bus are shared with the upper 16 bits of the a multiplicand input bus of the multiplier. similarly, the upper 16 bits of port b's data input bus are shared with the b multiplicand input bus of the multiplier. the internal structure of the block ram the block ram has a dual port structure. the two identical data ports called a and b permit independent access to the common block ram, which has a maximum capacity of 18,432 bits, or 16,384 bits with no parity bits (see parity bits description in ta b l e 2 2 ). each port has its own dedicated set of data, control, and clock lines for synchronous read and write operations. there are four basic data paths, as shown in figure 30 : 1. write to and read from port a 2. write to and read from port b 3. data transfer from port a to port b 4. data transfer from port b to port a number of ports a choice among primitives determines whether the block ram functions as dual- or single-port memory. a name of the form ramb16_s[w a ]_s[w b ] calls out the dual-port prim- itive, where the integers w a and w b specify the total data path width at ports a and b, respectively. thus, a ramb16_s9_s18 is a dual-port ram with a 9-bit port a and an 18-bit port b. a name of the form ramb16_s[w] identifies the single-port primitive, where the integer w specifies the total data path width of the lone port a. a ramb16_s18 is a single-port ram with an 18-bit port. port aspect ratios each port of the block ram can be configured indepen- dently to select a number of different possible widths for the data input (di) and data output (do) signals as shown in ta b l e 2 2 . ta bl e 2 1 : number of ram blocks by device device total number of ram blocks total addressable locations (bits) number of columns xc3s100e 4 73,728 1 xc3s250e 12 221,184 2 xc3s500e 20 368,640 2 xc3s1200e 28 516,096 2 xc3s1600e 36 663,552 2 figure 30: block ram data paths DS312-2_01_020705 spartan-3e dual-port block ram read 3 read write write read write write read port a port b 2 1 4 functional description 36 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r if the data bus width of port a differs from that of port b, the block ram automatically performs a bus-matching function as described in figure 31 . when data is written to a port with a narrow bus and then read from a port with a wide bus, the latter port effectively combines ?narrow? words to form ?wide? words. similarly, when da ta is written into a port with a wide bus and then read from a port with a narrow bus, the latter port divides ?wide? words to form ?narrow? words. par- ity bits are not available if the data port width is configured as x4, x2, or x1. for example, if a x36 data word (32 data, 4 parity) is addressed as two x18 halfwords (16 data, 2 par- ity), the parity bits associated with each data byte are mapped within the block ram to the appropriate parity bits. the same effect happens when the x36 data word is mapped as four x9 words. ta bl e 2 2 : port aspect ratios total data path width (w bits) di/do data bus width (w-p bits) 1 dip/dop parity bus width (p bits) addr bus width (r bits) 2 di/do [w-p-1:0] dip/dop [p-1:0] addr [r-1:0] no. of addressable locations (n) 3 block ram capacity (w*n bits) 4 1 1 0 14 [0:0] - [13:0] 16,384 16,384 2 2 0 13 [1:0] - [12:0] 8,192 16,384 4 4 0 12 [3:0] - [11:0] 4,096 16,384 9 8 1 11 [7:0] [0:0] [10:0] 2,048 18,432 18 16 2 10 [15:0] [1:0] [9:0] 1,024 18,432 36 32 4 9 [31:0] [3:0] [8:0] 512 18,432 notes: 1. the width of the total data path (w) is the sum of the di/do bus width (w-p) and any parity bits (p). 2. the width selection made for the di/do bu s determines the number of address lines (r) according to the rela tionship expressed as: r = 14 ? [log(w?p)/log(2)]. 3. the number of address lines delimits the total number (n) of addressable locations or depth according to the following equati on: n = 2 r . 4. the product of w and n yields the total block ram capacity. functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 37 product specification r figure 31: data organization and bus-matching operation with different port widths on port a and port b byte 0 byte 1 byte 2 byte 3 byte 0 byte 1 byte 2 byte 3 byte 0 byte 1 byte 2 byte 3 0 1 2 3 4 5 6 7 b y t e 3 0 0 1 0 1 2 3 0 1 6 7 0 1 2 3 4 5 6 7 byte 0 0 1 2 3 4 5 6 7 byte 3 0 1 2 3 p0 p2 p0 p1 p2 p3 p2 p3 p0 p1 p3 p1 0 1 2 3 byte 0 4 5 6 7 byte 3 0 1 2 3 c d e f 1c 1d 1e 1f 16 17 8 15 0 8 16 24 32 33 34 35 31 23 15 7 0 7 0 7 8 2 3 0 1 2 3 4 5 6 7 y t e 0 0 1 0 1 0 address 512x36 1kx18 2kx9 4kx4 8kx2 16kx1 parity data b DS312-2_02_102105 no parity (16kbits data) parity optional (16kbits data, 2kbits parity) functional description 38 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r block ram port signal definitions representations of the dual-port primitive ramb16_s[w a ]_s[w b ] and the single-port primitive ramb16_s[w] with their associated signals are shown in figure 32a and figure 32b , respectively. these signals are defined in ta b l e 2 3 . the control signals (we, en, clk, and ssr) on the block ram are active high. however, optional inverters on the control signals change the polarity of the active edge to active low. design note whenever a block ram port is enabled (ena or enb = high), all address transitions must meet the data sheet setup and hold times with respect to the port clock (clka or clkb), as shown in table 103, page 142 .this requirement must be met even if the ram read output is of no interest. figure 32: block ram primitives DS312-2_03_111105 wea e n a ssra clka addra[r a ?:0] dia[ w a ? a ?:0] dipa[p a ?:0] dopa[p a ?:0] doa[ w a ? a ?:0] ramb16_s w a _s w b (a) dual-port (b) sin g le-port dopb[p b ?:0] dob[ w b ? b ?:0] web e n b ssrb clkb addrb[r b ?:0] dib[ w b ? b ?:0] dipb[p b ?:0] we e n ssr clk addr[r?:0] di[ w ??:0] dip[p?:0] dop[p?:0] do[ w ??:0] ramb16_s w notes: 1. w a and w b are integers representing the total data path width (i.e., data bits plus parity bits) at ports a and b, respectively. 2. p a and p b are integers that indicate the number of data path lines serving as parity bits. 3. r a and r b are integers representing the address bus width at ports a and b, respectively. 4. the control signals clk, we, en, and ssr on both ports have the option of inverted polarity. functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 39 product specification r ta bl e 2 3 : block ram port signals signal description port a signal name port b signal name direction function address bus addra addrb input the address bus select s a memory location for read or write operations. the width (w) of the port?s associated data path determines the number of available address lines (r), as per ta b l e 2 2 . whenever a port is enabled (ena or enb = high), address transitions must meet the data sheet setup and hold times with respect to the port clock (clka or clkb), as shown in table 103, page 142 .this requirement must be met even if the ram read output is of no interest. data input bus dia dib input data at the di input bus is written to the ram location specified by the address input bus (addr) during the active edge of the clk input, when the clock enable (en) and write enable (we) inputs are active. it is possible to configure a port?s di input bus width (w-p) based on ta b l e 2 2 . this selection applies to both the di and do paths of a given port. parity data input(s) dipa dipb input parity inputs represent additi onal bits included in the data input path. although referred to herein as ?parity? bits, the parity inputs and outputs have no special functionality for generat ing or checking parity and can be used as additional data bits. the number of parity bits ?p? included in the di (same as for the do bus) depends on a port?s total data path width (w). see ta b l e 2 2 . data output bus doa dob output data is written to the do output bus from th e ram location specified by the address input bus, addr. see the di signal description for do port width configurations. basic data access occurs on the active edge of the clk when we is inactive and en is active. the do outputs mirror the data stored in the address addr memory location. data access with we active if the write_mode attribute is set to the value: write_first , which accesses data after the write takes place. read_first accesses data before the write occurs. a third attribute, no_change , latches the do outputs upon the assertion of we. see block ram data operations for details on the write_mode attribute. parity data output(s) dopa dopb output parity outputs represent additional bits includ ed in the data input path. the number of parity bits ?p? included in the di bus (same as for the do bus) depends on a port?s total data path width (w). see the dip signal description for configuration details. write enable wea web input when asserted together wi th en, this input enables the writing of data to the ram. when we is inactive with en asserted, read operations are still possible. in this case, a latch passes data from the addressed memory location to the do outputs. clock enable ena enb input when asserted, this input enables the clk signal to perform read and write operations to the block ram. when inactive, the block ram does not perform any read or write operations. set/reset ssra ssrb input when asserted, this pin forces the do output latch to the value of the srval attribute. it is synchronized to the clk signal. clock clka clkb input this input accepts the clock signal to which read and write operations are synchronized. all associated port inputs are required to meet setup times with respect to the clock signal?s active edge. the data output bus responds after a clock-to-out delay referenced to the clock signal?s active edge. functional description 40 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r block ram attribute definitions a block ram has a number of attributes that control its behavior as shown in ta b l e 2 4 . block ram data operations writing data to and accessing data from the block ram are synchronous operations that take place independently on each of the two ports. ta bl e 2 5 describes the data opera- tions of each port as a result of the block ram control sig- nals in their default active-high edges. the waveforms for the write operation are shown in the top half of figure 33 , figure 34 , and figure 35 . when the we and en signals enable the active edge of clk, data at the di input bus is written to the block ram location addressed by the addr lines. ta bl e 2 4 : block ram attributes function attribute possible values initial content for da ta memory, loaded during configuration initxx (init_00 through init3f) each initialization string defines 32 hex values of the 16384-bit data memory of the block ram. initial content for parity memory, loaded during configuration initpxx (initp_00 through initp0f) each initialization string defines 32 hex values of the 2048-bit parity data memory of the block ram. data output latch initialization init (single-port) inita , initb (dual-port) hex value the width of the chosen port. data output latch synchronous set/reset value srval (single-port) srval_a , srval_b (dual-port) hex value the width of the chosen port. data output latch behavior during write (see block ram data operations ) write_mode write_first, read_first, no_change ta bl e 2 5 : block ram function table input signals output signals ram data gsr en ssr we clk addr dip di dop do parity data immediately after configuration loaded during configuration x x initp_xx init_xx global set/reset immediately after configuration 1xxxx x x x init init no chg no chg ram disabled 0 0 x x x x x x no chg no chg no chg no chg synchronous set/reset 0110 x x x srval srval no chg no chg synchronous set/reset during write ram 0111 addr pdata data srval srval ram(addr) pdata ram(addr) data read ram, no write operation 0100 addr x x ram(pdata) ram(data) no chg no chg functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 41 product specification r there are a number of different conditions under which data can be accessed at the do outputs. basic data access always occurs when the we input is inactive. under this condition, data stored in the memory location addressed by the addr lines passes through a output latch to the do outputs. the timing for basic data access is shown in the portions of figure 33 , figure 34 , and figure 35 during which we is low. data also can be accessed on the do outputs when assert- ing the we input based on the value of the write_mode attribute as described in ta bl e 2 6 . write ram, simultaneous read operation 0101 addr pdata data write_mode = write_first pdata data ram(addr) pdata ram(addr) data write_mode = read_first ram(data) ram(data) ram(addr) pdata ram(addr) pdata write_mode = no_change no chg no chg ram(addr) pdata ram(addr) pdata ta bl e 2 5 : block ram function table (continued) input signals output signals ram data gsr en ssr we clk addr dip di dop do parity data ta bl e 2 6 : write_mode effect on data output latches during write operations write mode effect on same port effect on opposite port (dual-port only with same address) write_first read after write data on di and dip inputs is written into specified ram location and simultaneously appears on do and dop outputs. invalidates data on do and dop outputs. read_first read before write data from specified ram location appears on do and dop outputs. data on di and dip inputs is written into specified location. data from specified ram location appears on do and dop outputs. no_change no read on write data on do and do p outputs remains unchanged. data on di and dip inputs is written into specified location. invalidates data on do and dop outputs. functional description 42 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r setting the write_mode attribute to a value of write_first , data is written to the addressed memory location on an enabled active clk edge and is also passed to the do outputs. write_first timing is shown in the portion of figure 33 during which we is high. setting the write_mode attribute to a value of read_first , data already stored in the addressed loca- tion passes to the do outputs before that location is over- written with new data from the di inputs on an enabled active clk edge. read_first timing is shown in the por- tion of figure 34 during which we is high. figure 33: waveforms of block ram data operations with write_first selected clk w e di addr do en disabled read xxxx 1111 2222 xxxx aa bb cc dd 0000 mem(aa) 1111 2222 mem(dd) read w rite mem( bb )=1111 w rite mem(cc)=2222 DS312-2_05_020905 data_in internal memory do data_o u t = data_in di figure 34: waveforms of block ram data operations with read_first selected clk w e di addr do en disabled read xxxx 1111 2222 xxxx aa bb cc dd 0000 mem(aa) old mem( bb ) old mem(cc) mem(dd) read w rite mem( bb )=1111 w rite mem(cc)=2222 DS312-2_06_020905 data_in internal memory do prior stored data di functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 43 product specification r setting the write_mode attribute to a value of no_change , puts the do outputs in a latched state when asserting we. under this cond ition, the do outputs retain the data driven just before we is asserted. no_change timing is shown in the portion of figure 35 during which we is high. figure 35: waveforms of block ram data op erations with no_change selected clk w e di addr do en disabled read xxxx 1111 2222 xxxx aa bb cc dd 0000 mem(aa) mem(dd) read w rite mem( bb )=1111 w rite mem(cc)=2222 DS312-2_07_020905 data_in internal memory do no change d u ring write di functional description 44 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r dedicated multipliers for additional information, refer to the ? using embedded multipliers ? chapter in ug331 . the spartan-3e devices provide 4 to 36 dedicated multiplier blocks per device. the multipliers are located together with the block ram in one or two columns depending on device density. see arrangement of ram blocks on die for details on the location of these blocks and their connectivity. operation the multiplier blocks primarily perform two?s complement numerical multiplication but can also perform some less obvious applications, such as simple data storage and bar- rel shifting. logic slices also implement effici ent small multi- pliers and thereby supplement the dedicated multipliers. the spartan-3e dedicated multiplier blocks have additional features beyond those provided in spartan-3 fpgas. each multiplier performs the principle operation p = a b, where ?a? and ?b? are 18-bit words in two?s complement form, and ?p? is the full-precision 36-bit product, also in two?s complement form. the 18-bit inputs represent values rang- ing from -131,072 10 to +131,071 10 with a resulting product ranging from -17,179,738,112 10 to +17,179,869,184 10 . implement multipliers with in puts less than 18 bits by sign-extending the inputs (i.e., replicating the most-signifi- cant bit). wider multiplication operations are performed by combining the dedicated multip liers and slice-based logic in any viable combination or by time-sharing a single multi- plier. perform unsigned mult iplication by re stricting the inputs to the positive range. tie the most-significant bit low and represent the unsigned value in the remaining 17 lesser-significant bits. optional pipeline registers as shown in figure 36 , each multiplier block has optional registers on each of the multiplier inputs and the output. the registers are named areg, breg, and preg and can be used in any combination. the clock input is common to all the registers within a block, but each register has an inde- pendent clock enable and synchronous reset controls mak- ing them ideal for storing data samples and coefficients. when used for pipelining, the registers boost the multiplier clock rate, beneficial for higher performance applications. figure 36 illustrates the principle fe atures of the multiplier block. use the mult18x18sio primitive shown in figure 37 to instantiate a multiplier within a design. although high-level logic synthesis software usually automatically infers a multi- plier, adding the pipeline registers might require the mult18x18sio primitive. connect the appropriate signals to the mult18x18sio multiplier ports and set the individual areg, breg, and preg attributes to ?1? to insert the asso- ciated register, or to 0 to remove it and make the signal path combinatorial. figure 36: principle ports and functions of dedicated multiplier blocks x ce cea areg (optional) breg (optional) rsta a[17:0] p[35:0] dq rst ce cep preg (optional) rstp dq rst ce ceb rstb b[17:0] clk dq rst DS312-2_27_021205 functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 45 product specification r cascading multipliers the mult18x18sio primitive has two additional ports called bcin and bcout to cascade or share the multi- plier?s ?b? input among severa l multiplier bocks. the 18-bit bcin ?cascade? input port offers an alternate input source from the more typical ?b? input. the b_input attribute spec- ifies whether the specific implementation uses the bcin or ?b? input path. setting b_inpu t to direct chooses the ?b? input. setting b_input to ca scade selects the alternate bcin input. the breg register then optionally holds the selected input value, if required. bcout is an 18-bit output port that always reflects the value that is applied to the multiplier?s second input, which is either the ?b? input, the cascaded value from the bcin input, or the output of the breg if it is inserted. figure 38 illustrates the four possib le configurations using different settings for the b_input attribute and the breg attribute. figure 37: mult18x18sio primitive mult18x18sio a[17:0] p[35:0] bcout[17:0] b[17:0] cea ceb cep clk rsta rstb rstp bcin[17:0] DS312-2_2 8 _021205 figure 38: four configurations of the b input x ce ceb rstb bcin[17:0] bcin[17:0] clk dq rst bcout[17:0] breg = 1 b_input = cascade breg = 0 b_input = cascade x ce ceb rstb b[17:0] breg breg clk dq rst bcout[17:0] breg = 1 b_input = direct x bcout[17:0] b[17:0] breg = 0 b_input = direct x bcout[17:0] DS312-2_29_021505 functional description 46 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r the bcin and bcout ports have associated dedicated routing that connects adjac ent multipliers within the same column. via the cascade connection, the bcout port of one multiplier block drives the bcin port of the multiplier block directly above it. there is no connection to the bcin port of the bottom-most multiplier block in a column or a connection from the bcout port of the top-most block in a column. as an example, figure 39 shows the multiplier cas- cade capability within the xc3s100e fpga, which has a single column of multiplier, four blocks tall. for clarity, the figure omits the register control inputs. when using the breg register, the cascade connection forms a shift register structure typically used in dsp algo- rithms such as direct-form fir filters. when the breg reg- ister is omitted, the cascade structure essentially feeds the same input value to more than one multiplier. this parallel connection serves to create wide-input multipliers, imple- ment transpose fir filters, and is used in any application that requires that several mu ltipliers have the same input value. multiplier/block ram interaction each multiplier is located adja cent to an 18 kbit block ram and shares some interconnect resources. configuring an 18 kbit block ram for 36-bit wide data (512 x 36 mode) pre- vents use of the associated dedicated multiplier. the upper 16 bits of the ?a? multiplicand input are shared with the upper 16 bits of the block ram?s port a data input. similarly, the upper 16 bits of the ?b? multiplicand input are shared with port b?s data input. see also figure 48, page 64 . figure 39: multiplier cascade connection bcout bcin b_input = cascade a p b a b a b a b DS312-2_30_021505 bcout bcin b_input = cascade p bcout bcin b_input = cascade p bcout bcin b_input = direct p functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 47 product specification r ta bl e 2 7 defines each port of the mult18x18sio primitive. ta bl e 2 7 : mult18x18sio embedded multiplier primitives description signal name direction function a[17:0] input the primary 18-bit two?s complement value for multiplication. the block multiplies by this value asynchronously if the optional areg and preg registers are omitted. when areg and/or preg are used, the value provided on this port is qualified by the rising edge of clk, subject to the appropriate register controls. b[17:0] input the second 18-bit two?s complement value for multiplication if the b_input attribute is set to direct. the block multiplies by th is value asynchronously if the optional breg and preg registers are omitted. when breg and/or preg are used, the value provided on this port is qualified by the rising edge of clk, subject to the appropriate register controls. bcin[17:0] input the second 18-bit two?s complement value for multiplication if the b_input attribute is set to cascade. the block multiplies by this value asynchronously if the optional breg and preg registers are omitted. when breg and/or preg are used, the value provided on this port is qualified by the rising edge of clk, subject to the appropriate register controls. p[35:0] output the 36-bit two?s complement product resulting from the multiplication of the two input values applied to the multiplier. if the optional areg, breg and preg registers are omitted, the output operates asynchronously. use of preg causes this output to respond to the rising edge of clk with the value qualified by cep and rstp. if preg is omitted, but areg and breg are used, th is output responds to the rising edge of clk with the value qualified by cea, rsta, ceb, and rstb. if preg is omitted and only one of areg or breg is used, this output responds to both asynchronous and synchronous events. bcout[17:0] output the value being applied to the second input of the multiplier. when the optional breg register is omitted, this output responds asynchronously in response to changes at the b[17:0] or bcin[17:0] ports according to the setting of the b_input attribute. if breg is used, this output responds to the rising edge of clk with the value qualified by ceb and rstb. cea input clock enable qualifier for the optional areg register. the value provided on the a[17:0] port is captured by areg in response to a rising edge of clk when this signal is high, provided that rsta is low. rsta input synchronous reset for the optional areg register. areg content is forced to the value zero in response to a rising edge of clk when this signal is high. ceb input clock enable qualifier for the optional breg register. the value provided on the b[17:0] or bcin[17:0] port is captured by breg in response to a rising edge of clk when this signal is high, provided that rstb is low. rstb input synchronous reset for the optional breg register. breg content is forced to the value zero in response to a rising edge of clk when this signal is high. cep input clock enable qualifier for the optional preg register. the value provided on the output of the multiplier port is captured by preg in response to a rising edge of clk when this signal is high, provided that rstp is low. rstp input synchronous reset for the optional preg register. preg content is forced to the value zero in response to a rising edge of clk when this signal is high. notes: 1. the control signals clk, cea, rsta, ceb, rstb, ce p, and rstp have the option of inverted polarity. functional description 48 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r digital clock managers (dcms) for additional information, refer to the using digital clock managers (dcms) chapter in ug331 . differences from the spartan-3 architecture ? spartan-3e fpgas have two, four, or eight dcms, depending on device size. ? the variable phase shifting feature functions differently on spartan-3e fpgas than from spartan-3 fpgas. ? the spartan-3e dlls support lower input frequencies, down to 5 mhz. spartan-3 dlls support down to 18 mhz. overview spartan-3e fpga digital clock managers (dcms) provide flexible, complete control over clock frequency, phase shift and skew. to accomplish this, the dcm employs a delay-locked loop (dll), a fully digital control system that uses feedback to maintain clock signal characteristics with a high degree of precision despite normal variations in oper- ating temperature and voltage. this section provides a fun- damental description of the dcm. the xc3s100e fpga has two dcms, one at the top and one at the bottom of the device. the xc3s250e and xc3s500e fpgas each include four dcms, two at the top and two at the bottom. the xc3s1200e and xc3s1600e fpgas contain eight dcms with two on each edge (see also figure 45 ). the dcm in spartan-3e fpgas is sur- rounded by clbs within the logic array and is no longer located at the top and bottom of a column of block ram as in the spartan-3 architecture. the digital clock manager is instantiated within a design using a ?dcm? primitive. the dcm supports three major functions: ? clock-skew elimination: clock skew within a system occurs due to the different arrival times of a clock signal at different points on the die, typically caused by the clock signal distribution network. clock skew increases setup and hold time requirements and increases clock-to-out times, all of which are undesirable in high frequency applications. th e dcm eliminates clock skew by phase-aligning the output clock signal that it generates with the incoming clock signal. this mechanism effectively cancels out the clock distribution delays. ? frequency synthesis: the dcm can generate a wide range of different output clock frequencies derived from the incoming clock signal. this is accomplished by either multiplying and/or dividing the frequency of the input clock signal by any of several different factors. ? phase shifting: the dcm provides the ability to shift the phase of all its output clock signals with respect to the input clock signal. although a single design primitive, the dcm consists of four interrelated functional units: the delay-locked loop (dll), the digital frequency synthesizer (dfs), the phase shifter (ps), and the status logic. each component has its associ- ated signals, as shown in figure 40 . figure 40: dcm functional blocks and associated signals d s 099-2_07_101205 p s incdec p s en p s clk clkin clkfb r s t s tat u s [7:0] locked 8 clkfx1 8 0 clkfx clk0 p s done clock di s tri bu tion del a y clk90 clk1 8 0 clk270 clk2x clk2x1 8 0 clkdv statu s logic dfs dll pha s e shifter del a y s tep s o u tp u t s t a ge inp u t s t a ge dcm functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 49 product specification r delay-locked loop (dll) the most basic function of the dll component is to elimi- nate clock skew. the main signal path of the dll consists of an input stage, followed by a series of discrete delay ele- ments or steps, which in turn leads to an output stage. this path together with logic for phase detection and control forms a system complete with feedback as shown in figure 41 . in spartan-3e fpgas, the dll is implemented using a counter-based delay line. the dll component has two clock inputs, clkin and clkfb, as well as seven clock outputs, clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv as described in ta b l e 2 8 . the clock outputs drive simulta- neously. signals that initialize and report the state of the dll are discussed in status logic . the clock signal supplied to the clkin input serves as a reference waveform. the dll seeks to align the rising-edge of feedback signal at the clkfb input with the rising-edge of clkin input. wh en eliminating clock skew, the common approach to using the dll is as follows: the clk0 signal is passed through the clock distribution network that feeds all the registers it synchronizes. these registers are either internal or external to the fpga. after passing through the figure 41: simplified functional diagram of dll ds099-2_0 8 _041103 clkin delay n clkfb rst clk0 clk90 clk1 8 0 clk270 clk2x clk2x1 8 0 clkdv o u tp u t section control delay n-1 phase detection locked delay 2 delay 1 ta bl e 2 8 : dll signals signal direction description clkin input receives the incoming clock signal. see ta bl e 3 0 , ta b l e 3 1 , and ta bl e 3 2 for optimal external inputs to a dcm. clkfb input accepts either clk0 or clk2x as the feedback signal. (set the clk_feedback attribute accordingly). clk0 output generates a clock signal with the same frequency and phase as clkin. clk90 output generates a clock signal with the same frequency as clkin, phase-shifted by 90. clk180 output generates a clock signal with the same frequency as clkin, phase-shifted by 180. clk270 output generates a clock signal with the same frequency as clkin, phase-shifted by 270. clk2x output generates a clock signal with the same phase as clkin, and twice the frequency. clk2x180 output generates a clock signal with twice the frequency of clkin, and phase-shifted 180 with respect to clk2x. clkdv output divides the clkin frequency by clkdv_divide value to generate lower frequency clock signal that is phase-aligned to clkin. functional description 50 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r clock distribution network, the clock signal returns to the dll via a feedback line called clkfb. the control block inside the dll measures the phase error between clkfb and clkin. this phase error is a measure of the clock skew that the clock distribution network introduces. the control block activates the appropriate number of delay steps to cancel out the clock skew. when the dll phase-aligns the clk0 signal with the clkin signal, it asserts the locked output, indicating a lock on to the clkin signal. dll attributes and related functions the dll unit has a variety of associated attributes as described in ta bl e 2 9 . each attribute is described in detail in the sections that follow. dll clock input connections for best results, an external clock source enters the fpga via a global clock input (gclk). each specific dcm has four possible direct, optimal gclk inputs that feed the dcm?s clkin input, as shown in ta b l e 3 0 . ta bl e 3 0 also provides the specific pin numbers by package for each gclk input. the two additional dcm?s on the xc3s1200e and xc3s1600e have similar optimal connections from the left-edge lhclk and the ri ght-edge rhclk inputs, as described in ta b l e 3 1 and ta b l e 3 2 . ? the dcm supports differential clock inputs (for example, lvds, lvpecl_25) via a pair of gclk inputs that feed an internal single-ended signal to the dcm?s clkin input. design note avoid using global clock input gclk1 as it is always shared with the m2 mode select pin. global clock inputs gclk0, gclk2, gclk3, gclk12, gclk13, gclk14, and gclk15 have shared functionality in some configuration ta bl e 2 9 : dll attributes attribute description values clk_feedback chooses either the clk0 or clk2x output to drive the clkfb input none, 1x , 2x clkin_divide_by_2 halves the frequency of the clkin signal just as it enters the dcm false , true clkdv_divide selects the constant used to divide the clkin input frequency to generate the clkdv output frequency 1.5, 2 , 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6.0, 6.5, 7.0, 7.5, 8, 9, 10, 11, 12, 13, 14, 15, and 16 clkin_period additional information that allows the dll to operate with the most efficient lock time and the best jitter tolerance floating-point value representing the clkin period in nanoseconds functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 51 product specification r ta bl e 3 0 : direct clock input connections and optional external feedback to associated dcms package differential pair differential pair differential pair differential pair npnp npnp pin number for single-ended input pin number for single-ended input vq100 p91 p90 p89 p88 p86 p85 p84 p83 cp132 b7 a7 c8 b8 a9 b9 c9 a10 tq144 p131 p130 p129 p128 p126 p125 p123 p122 pq208 p186 p185 p184 p183 p181 p180 p178 p177 ft256 d8 c8 b8 a8 a9 a10 f9 e9 fg320 d9 c9 b9 b8 a10 b10 e10 d10 fg400 a9 a10 g10 h10 e10 e11 g11 f11 fg484 b11 c11 h11 h12 c12 b12 e12 f12 associated gl obal buffers gclk11 gclk10 gclk9 gclk8 bufgmux_x1y10 bufgmux_x1y11 bufgmux_x2y10 bufgmux_x2y11 gclk7 gclk6 gclk5 gclk4 top left dcm xc3s100: n/a xc3s250e, xc3s500e: dcm_x0y1 xc3s1200e, xc3s1600e: dcm_x1y3 top right dcm xc3s100: dcm_x0y1 xc3s250e, xc3s500e: dcm_x1y1 xc3s1200e, xc3s1600e: dcm_x2y3 h g f e clock line (see ta bl e 4 1 ) d c b a bottom left dcm xc3s100: n/a xc3s250e, xc3s500e: dcm_x0y0 xc3s1200e, xc3s1600e: dcm_x1y0 bufgmux_x1y0 bufgmux_x1y1 bufgmux_x2y0 bufgmux_x2y1 bottom right dcm xc3s100: dcm_x0y0 xc3s250e, xc3s500e: dcm_x1y0 xc3s1200e, xc3s1600e: dcm_x2y0 gclk12 gclk13 gclk14 gclk15 gclk0 gclk1 gclk2 gclk3 associated gl obal buffers package differential pair differential pair differential pair differential pair pnpn pnpn pin number for single-ended input pin number for single-ended input vq100 p32 p33 p35 p36 p38 p39 p40 p41 cp132 m4 n4 m5 n5 m6 n6 p6 p7 tq144 p50 p51 p53 p54 p56 p57 p58 p59 pq208 p74 p75 p77 p78 p80 p81 p82 p83 ft256 m8 l8 n8 p8 t9 r9 p9 n9 fg320 n9 m9 u9 v9 u10 t10 r10 p10 fg400 w9 w10 r10 p10 p11 p12 v10 v11 fg484 v11 u11 r11 t11 r12 p12 y12 w12 functional description 52 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r ta bl e 3 1 : direct clock input and optional external feedback to left-edge dcms (xc3s1200e and xc3s1600e) diff. clock single-ended pin number by package type left edge vq100 cp132 tq144 pq208 ft256 fg320 fg400 fg484 lhclk dcm/bufgmux bufgmux_x0y5 d bufgmux_x0y4 c pair p p9 f3 p14 p22 h5 j5 k3 m5 lhclk0 dcm_x0y2 clock lines n p10f2p15p23h6 j4 k2 l5 lhclk1 pair p p11f1p16p24h3 j1 k7 l8 lhclk2 n p12g1p17p25h4 j2 l7 m8 lhclk3 bufgmux_x0y3 b bufgmux_x0y2 a bufgmux_x0y9 h bufgmux_x0y8 g pair p p15g3p20p28 j2 k3 m1 m1 lhclk4 dcm_x0y1 clock lines n p16h1p21p29 j3 k4 l1 n1 lhclk5 pair p p17h2p22p30 j5 k6 m3 m3 lhclk6 n p18h3p23p31 j4 k5 l3 m4 lhclk7 bufgmux_x0y7 f bufgmux_x0y6 e ta bl e 3 2 : direct clock input and optional external feedba ck to right-edge dcms (xc3s1200e and xc3s1600e) right edge single-ended pin number by package type diff. clock dcm/bufgmux rhclk vq100 cp132 tq 144 pq208 ft256 fg320 fg400 fg484 d ? bufgmux_x3y5 c ? bufgmux_x3y4 clock lines dcm_x3y2 rhclk7 ? p68 g13 p94 p135 h11 j14 j20 l19 n pair rhclk6 ? p67 g14 p93 p134 h12 j15 k20 l18 p rhclk5 ? p66 h12 p92 p133 h14 j16 k14 l21 n pair rhclk4 ? p65 h13 p91 p132 h15 j17 k13 l20 p b ? bufgmux_x3y3 a ? bufgmux_x3y2 h ? bufgmux_x3y9 g ? bufgmux_x3y8 clock lines dcm_x3y1 rhclk3 ? p63 j14 p88 p129 j13 k14 l14 m16 n pair rhclk2 ? p62 j13 p87 p128 j14 k15 l15 m15 p rhclk1 ? p61 j12 p86 p127 j16 k12 l16 m22 n pair rhclk0 ? p60 k14 p85 p126 k16 k13 m16 n22 p f ? bufgmux_x3y7 e ? bufgmux_x3y6 functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 53 product specification r every fpga input provides a possible dcm clock input, but the path is not temperature and voltage compensated like the gclks. alternatively, clock signals within the fpga optionally provide a dcm clock input via a global clock multiplexer buffer (bufgmux). the global clock net con- nects directly to the clkin input. the internal and external connections are shown in figure 42a and figure 42c , respectively. dll clock output and feedback connections as many as four of the nine dcm clock outputs can simulta- neously drive four of the bufgmux buffers on the same die edge. all dcm clock outputs can simultaneously drive gen- eral routing resources, including interconnect leading to obuf buffers. the feedback loop is essential for dll operation. either the clk0 or clk2x outputs feed back to the clkfb input via a bufgmux global buffer to eliminate the clock distribution delay. the specific bufgmux buffer used to feed back the clk0 or clk2x signal is ideally one of the bufgmux buff- ers associated with a specific dcm, as shown in ta bl e 3 0 , ta bl e 3 1 , and ta bl e 3 2 . the feedback path also phase-aligns the other seven dll outputs: clk0, clk90, clk1 80, clk270, clkdv, clk2x, or clk2x180. the clk_feedback attribute value must agree with the physical feedback connection. use ?1x? for clk0 feedback and ?2x? for clk2x feedback. if the dfs unit is used stand-alone, without the dll, then no feedback is required and set the clk_feedback attribute to ?none?. two basic cases determine how to connect the dll clock outputs and feedback connections: on-chip synchronization and off-chip synchronization, which are illustrated in figure 42a through figure 42d . in the on-chip synchro nization case in figure 42a and figure 42b , it is possible to connect any of the dll?s seven output clock signals through general routing resources to the fpga?s internal registers. either a global clock buffer (bufg) or a bufgmux affords access to the global clock network. as shown in figure 42a , the feedback loop is cre- ated by routing cl k0 (or clk2x) in figure 42b to a global clock net, which in turn drives the clkfb input. in the off-chip synch ronization case in figure 42c and figure 42d , clk0 (or clk2x) plus any of the dll?s other output clock signals exit the fpga using output buffers (obuf) to drive an external clock network plus registers on the board. as shown in figure 42c , the feedback loop is formed by feeding clk0 (or clk2x) in figure 42d back into the fpga, then to the dcm?s clkfb input via a global buffer input, specified in ta bl e 3 0 . figure 42: input clock, output clock, and feedback connections for the dll ds099-2_09_0 8 2104 clk90 clk1 8 0 clk270 clkdv clk2x clk2x1 8 0 clk0 clk0 clock net delay bufgmux bufgmux bufg fpga (a) on-chip with clk0 feedback clkin dcm clkfb clk90 clk1 8 0 clk270 clkdv clk2x clk2x1 8 0 clk0 clk0 clock net delay ibufg ibufg fpga (c) off-chip with clk0 feedback clkin dcm clkfb obuf obuf clk2x clk2x ibufg ibufg fpga (d) off-chip with clk2x feedback clkin dcm clkfb obuf obuf clk0 clk90 clk1 8 0 clk270 clkdv clk2x1 8 0 clk2x clk2x clock net delay clock net delay bufgmux bufgmux bufg fpga (b) on-chip with clk2x feedback clkin dcm clkfb clk0 clk90 clk1 8 0 clk270 clkdv clk2x1 8 0 functional description 54 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r accommodating input frequencies beyond spec- ified maximums if the clkin input frequency exceeds the maximum permit- ted, divide it down to an acceptable value using the clkin_divide_by_2 attribute. w hen this attribute is set to ?true?, the clkin frequency is divided by a factor of two as it enters the dcm. in addition, the clkin_divide_by_2 option produces a 50% duty -cycle on the input clock, although at half the clkin frequency. quadrant and half-period phase shift outputs in addition to clk0 for zero-phase alignment to the clkin signal, the dll also provides the clk90, clk180, and clk270 outputs for 90, 180, and 270 phase-shifted sig- nals, respectively. these signals are described in table 28, page 49 and their relative timing is shown in figure 43 . for control in finer increments than 90, see phase shifter (ps) . basic frequency synthesis outputs the dll component provides basic options for frequency multiplication and division in addition to the more flexible synthesis capability of the df s component, de scribed in a later section. these operations result in output clock signals with frequencies that are either a fraction (for division) or a multiple (for multiplication) of the incoming clock frequency. the clk2x output produces an in-phase signal that is twice the frequency of clkin. the clk2x180 output also dou- bles the frequency, but is 180 out-of-phase with respect to clkin. the clkdiv output generates a clock frequency that is a predetermined fraction of the clkin frequency. the clkdv_divide attribute determines the factor used to divide the clkin frequency. the attribute can be set to var- ious values as described in ta b l e 2 9 . the basic frequency synthesis outputs are described in ta bl e 2 8 . duty cycle correction of dll clock outputs the dll output signals exhibit a 50% duty cycle, even if the incoming clkin signal has a different duty cycle. fifty-per- cent duty cycle means that the high and low times of each clock cycle are equal. dll performance differences between steppings as indicated in digital clock manager (dcm) timing (module 3), the stepping 1 re vision silicon supports higher maximum input and output frequencies. stepping 1 devices are backwards compatible with stepping 0 devices. digital frequency synthesizer (dfs) the dfs unit generates clock signals where the output fre- quency is a product of the clkin input clock frequency and a ratio of two user-specified integers. the two dedicated outputs from the dfs unit, clkfx and clkfx180, are defined in ta b l e 3 3 . the signal at the clkfx180 output is essentially an inver- sion of the clkfx signal. thes e two outputs always exhibit a 50% duty cycle, even when the clkin signal does not. the dfs clock outputs are active coincident with the seven dll outputs and their output phase is controlled by the phase shifter unit (ps). the output frequency (f clkfx ) of the dfs is a function of the incoming clock frequency (f clkin ) and two integer attributes, as follows. eq. 1 the clkfx_multiply attribute is an integer ranging from 2 to 32, inclusive, and forms the numerator in equation 1 . figure 43: characteristics of the dll clock outputs output s i g nal - duty cycle corrected phase: input s i g nal (40%/60% duty cycle) 0 o 90 o 180 o 270 o 0 o 90 o 180 o 270 o 0 o ds099-2_10_101105 clkin t clk2x clk2x180 clkdv clk0 clk90 clk180 clk270 table 33: dfs signals signal direction description clkfx output multiplies the clkin frequency by the attribute-value ratio (clkfx_multiply/ clkfx_divide) to generate a clock signal with a new target frequency. clkfx180 output generates a clock signal with the same frequency as clkfx, but shifted 180 out-of-phase. f clkfx f clkin clkfx_multiply clkfx_divide --------------------------------------------------- - ?? ?? ? = functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 55 product specification r the clkfx_divide is an integer ranging from 1 to 32, inclusive and forms the denominator in equation 1 . for example, if clkfx_multiply = 5 and clkfx_divide = 3, the frequency of the output clock signal is 5/3 that of the input clock signal. these attributes and their acceptable ranges are described in ta b l e 3 4 . any combination of integer values can be assigned to the clkfx_multiply and clkfx_divide attributes, pro- vided that two conditions are met: 1. the two values fall within their corresponding ranges, as specified in ta b l e 3 4 . 2. the f clkfx output frequency calculated in equation 1 falls within the dcm?s operating frequency specifications (see ta bl e 1 0 7 in module 3). dfs with or without the dll although the clkin input is sh ared with both units, the dfs unit functions with or separately from the dll unit. separate from the dll, the dfs generates an output frequency from the clkin frequency according to the respective clkfx_multiply and clkfx_divide values. frequency synthesis does not require a feedback loop. furthermore, without the dll, the dfs unit supports a broader operating frequency range. with the dll, the dfs unit operates as described above, only with the additional benefit of eliminating the clock distri- bution delay. in this case, a feedback loop from the clk0 or clk2x output to the clkfb input must be present. when operating with the dll unit, the dfs?s clkfx and clkfx180 outputs are phase-aligned with the clkin input every clkfx_divide cycles of clkin and every clkfx_multiply cycles of clkfx. for example, when clkfx_multiply = 5 and clkfx_divide = 3, the input and output clock edges coincide every three clkin input periods, which is equivalent in time to five clkfx output periods. smaller clkfx_multiply and clkfx_divide values result in faster lock times. therefore, clkfx_multiply and clkfx_divide must be factored to reduce their values wherever possible. for example, given clkfx_multiply = 9 and clkfx_divide = 6, removing a factor of three yields clkfx_multiply = 3 and clkfx_divide = 2. while both value-pair s result in the multiplication of clock frequency by 3/2, the latter value-pair enables the dll to lock more quickly. phase shifter (ps) the dcm provides two approaches to controlling the phase of a dcm clock output signal relative to the clkin signal: first, eight of the nine dcm clock outputs ? clk0, clk90, clk180, clk270, clk2x, clk2x180, clkfx, and clkfx180 ? provide either quadrant or half-period phase shifting of the input clock. second, the ps unit provides additional fine phase shift control of all nine dcm outputs. the ps unit accomplishes this by introducing a ?fine phase shift? delay (t ps ) between the clkfb and clkin signals inside the dll unit. in fixed phase shift mode, the fine phase shift is specified at design time with a resolution down to 1 / 256 th of a clkin cycle or one delay step (dcm_delay_step), whichever is greater. this fine phase shift value is relative to the coarser quadrant or half-period phase shift of the dcm clock output. when used, the ps unit shifts the phase of all nine dcm clock out- put signals. enabling phase shifting and selecting an operat- ing mode the clkout_phase_shift attribute controls the ps unit for the specific dcm instantiation. as described in ta b l e 3 5 , this attribute has three possible values: none, fixed, and variable. when clkout_phase_shift = none, the ps unit is disabled and the dcm output clocks are phase-aligned to the clkin input via the clkfb feedback path. figure 44a shows this case. the ps unit is enabled wh en the clkout_phase_shift attribute is set to fixed or variable modes. these two modes are described in the sections that follow. ta bl e 3 4 : dfs attributes attribute description values clkfx_multiply frequency multiplier constant integer from 2 to 32, inclusive clkfx_divide frequency divisor constant integer from 1 to 32, inclusive ta bl e 3 5 : ps attributes attribute description values clkout_phase_shift disables the ps component or chooses between fixed phase and variable phase modes. none , fixed, variable phase_shift determines size and direct ion of initial fine phase shift. integers from ?255 to +255 functional description 56 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r fixed phase shift mode the fixed phase shift mode shifts the dcm outputs by a fixed amount (t ps ), controlled by the user-specified phase_shift attribute. the phase_shift value (shown as p in figure 44 ) must be an integer ranging from ?255 to +255. phase_shift specifies a phase shift delay as a fraction of the t clkin. the phase shift behavior is different between ise 8.1, service pack 3 and prior software ver- sions, as described below. design note prior to ise 8.1i, service pack 3, the fixed phase shift fea- ture operated differently than the spartan-3 dcm design primitive and simulation m odel. designs using software prior to ise 8.1i, service pack 3 require recompilation using the latest ise software re lease. the following answer record contains additional information: http://www.xilinx.com/supp ort/answers/23153.htm . fixed phase shift using ise 8.1i, service pack 3 and later: see equation 2 . the value corresponds to a phase shift range of ?360 to +360 , which matches behavior of the spartan-3 dcm design primitive and simulation model. eq. 2 fixed phase shift prior to ise 8.1i, service pack 3: see equation 3 . the value corresponds to a phase shift range of ?180 to +180 degrees, which is different from the spar- tan-3 dcm design primitive and simulation model. designs created prior to ise 8.1i, service pack 3 must be recom- piled using the most recent ise development software. eq. 3 when the phase_shift value is zero, clkfb and clkin are in phase, the same as when the ps unit is disabled. when the phase_shift value is positive, the dcm out- puts are shifted later in time with respect to clkin input. when the attribute value is negative, the dcm outputs are shifted earlier in time with respect to clkin. figure 44b illustrates the relation ship between clkfb and clkin in the fixed phase mode. in the fixed phase mode, the psen, psclk, and psincde c inputs ar e not used and must be tied to gnd. equation 2 or equation 3 applies only to fixed phase shift mode. the variable phase shift mode operates differ- ently. t ps phaseshift 256 ---------------------------------------- ?? ?? t clkin ? = t ps phaseshift 512 ---------------------------------------- ?? ?? t clkin ? = figure 44: none and fixed phase shifter waveforms (ise 8.1i, service pack 3 and later) DS312-2_61_021606 clkin clkfb * t clkin p 256 b. clkout_pha s e_ s hift = fixed shift range over all p values: ?255 +255 0 clkin clkfb a. clkout_pha s e_ s hift = none (via clk0 or clk2x feedback) (via clk0 or clk2x feedback) functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 57 product specification r variable phase shift mode in variable phase shift mode, the fpga application dynamically adjusts the fine phase shift value using three inputs to the ps unit (psen, psclk, and psincdec), as defined in ta b l e 3 6 and shown in figure 40 . the fpga application uses the three ps inputs on the phase shift unit to dynamica lly and incrementally increase or decrease the phase shift amount on all nine dcm clock outputs. to adjust the current phase shift value, the psen enable signal must be high to enable the ps unit. coincidently, psincdec must be high to increment the current phase shift amount or low to decrement the current amount. all variable phase shift operations are controlled by the psclk input, which can be the clkin signal or any other clock signal. design note the variable phase shift feature operates differently from the spartan-3 dcm but the dcm design primitive is com- mon to both spartan-3 and spartan-3e design entry. vari- able phase shift in spartan-3e fpgas behaves as described herein. however, the dcm design primitive and simulation model does not match this behavior. starting with ise 8.1i, service pack 3, using the variable attribute generates an error message. the following answer record describes how to re-enable the variable phase shift fea- ture. http://www.xilinx.com/supp ort/answers/23004.htm dcm_delay_step dcm_delay_step is the finest delay resolution available in the ps unit. its value is provided at the bottom of table 105 in module 3. for each enabled psclk cycle that psincdec is high, the ps unit adds one dcm_ delay_step of phase shift to all nine dcm outputs. simi- larly, for each enabled psclk cycle that psincdec is low, the ps unit subtracts one dcm_ delay_step of phase shift from all nine dcm outputs. because each dcm_delay_step has a minimum and maximum value, the actual phase shift delay for the present phase increment/decrement value (value) falls within the minimum and maximum values according to equation 4 and equation 5 . eq. 4 eq. 5 the maximum variable phase shift steps, max_steps, is described in equation 6 or equation 7 , for a given clkin input period, t clkin , in nanoseconds. to convert this to a phase shift range measured in time and not steps, use max_steps derived in equation 6 and equation 7 for value in equation 4 and equation 5 . if clkin < 60 mhz: eq. 6 if clkin > 60 mhz: eq. 7 the phase adjustment might require as many as 100 clkin cycles plus 3 psclk cycles to take effect, at which point the dcm?s psdone output goes high for one psclk cycle. this pulse indicates that the ps unit completed the previous adjustment and is now ready for the next request. asserting the reset (rst) input returns the phase shift to zero. ta bl e 3 6 : signals for variable phase mode signal direction description psen (1) input enables the phase shift unit for variable phase adjustment. psclk (1) input clock to synchronize phase shift adjustment. psincdec (1) input when high, increments the current phase shift value. when low, decrements the current phase shift value. this signal is synchronized to the psclk signal. psdone output goes high to indicate that the present phase adjustment is complete and ps unit is ready for next phase adjustment request. this signal is synchronized to the psclk signal. notes: 1. this input supports either a true or inverted polarity. t ps max () value dcm_delay_step_max ? = t ps min () value dcm_delay_step_min ? = max_steps integer 10 t clkin 3 ? () ? () [] = max_steps integer 15 t clkin 3 ? () ? () [] = functional description 58 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r status logic the status logic indicates the present state of the dcm and a means to reset the dcm to its initial known state. the status logic signals are described in ta bl e 3 7 . in general, the reset (rst) input is only asserted upon con- figuring the fpga or when changing the clkin frequency. the rst signal must be asserted for three or more clkin cycles. a dcm reset does not affect attribute values (for example, clkfx_multiply and clkfx_divide). if not used, rst is tied to gnd. the eight bits of the status bus are described in ta b l e 3 8 . stabilizing dcm clocks before user mode the startup_wait attribute shown in ta bl e 3 9 optionally delays the end of the fpga?s configuration process until after the dcm locks to its incoming clock frequency. this option ensures that the fpga remains in the startup phase of configuration until all clock outputs generated by the dcm are stable. when all dcms that have their startup_wait attribute set to true assert the locked signal, then the fpga completes its configuration process and proceeds to user mode. the associated bitstream gen- erator (bitgen) option lck_cycle specifies one of the six cycles in the startup phase. the selected cycle defines the point at which configuration st alls until all the locked out- puts go high. see start-up , page 107 for more information. spread spectrum dcms accept typical spread spectrum clocks as long as they meet the input requirem ents. the dll will track the fre- quency changes created by the spread spectrum clock to drive the global clocks to the fpga logic. see xapp469 , spread-spectrum clocking reception for displays for details. ta bl e 3 7 : status logic signals signal direction description rst input a high resets the entire dcm to its initial power-on state. initializes the dll taps for a delay of zero. sets the locked output low. this input is asynchronous. status[7:0] output the bit values on the status bus provide information regarding the state of dll and ps operation locked output indicates that the clkin and clkfb signals are in phase by going high. the two signals are out-of-phase when low. ta bl e 3 8 : dcm status bus bit name description 0 reserved - 1 clkin stopped when high, indicates that the clkin input signal is not toggling. when low, indicates clkin is toggling. this bit functions only when the clkfb input is connected. (1) 2 clkfx stopped when high, indicates that the clkfx output is not toggling. when low, indicates the clkfx output is toggling. this bit functions only when the clkfx or clkfx180 output are connected. 3-6 reserved - notes: 1. when only the dfs clock outputs but none of the dll clock outputs are used, this bit does not go high when the clkin signal s tops. table 39: startup_wait attribute attribute description values startup_wait when true, delays transition from configuration to user mode until dcm locks to the input clock. true, false functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 59 product specification r clocking infrastructure for additional information, refer to the using global clock resources chapter in ug331 . the spartan-3e clocking infrastructure, shown in figure 45 , provides a series of low-capacitance, low-skew interconnect lines well-suited to carrying high-frequency signals through- out the fpga. the infrastructure also includes the clock inputs and bufgmux clock buffers/multiplexers. the xilinx place-and-route (par) software automatically routes high-fanout clock signals using these resources. clock inputs clock pins accept external clock signals and connect directly to dcms and bufgmux elements. each spar- tan-3e fpga has: ? 16 global clock inputs (gclk0 through gclk15) located along the top and bottom edges of the fpga ? 8 right-half clock inputs (rhclk0 through rhclk7) located along the right edge ? 8 left-half clock inputs (lhclk0 through lhclk7) located along the left edge clock inputs optionally connect directly to dcms using ded- icated connections. ta b l e 3 0 , ta b l e 3 1 , and ta b l e 3 2 show the clock inputs that best feed a specific dcm within a given spartan-3e part number. different spartan-3e fpga densi- ties have different numbers of dcms. the xc3s1200e and xc3s1600e are the only two densities with the left- and right-edge dcms. each clock input is also optionally a user-i/o pin and con- nects to internal interconnect. some clock pad pins are input-only pins as indicated in pinout descriptions (mod- ule 4). design note avoid using global clock input gclk1 as it is always shared with the m2 mode select pin. global clock inputs gclk0, gclk2, gclk3, gclk12, gclk13, gclk14, and gclk15 have shared functionality in some configuration modes. clock buffers/multiplexers clock buffers/multiplexers either drive clock input signals directly onto a clock line (bufg) or optionally provide a mul- tiplexer to switch between two unrelated, possibly asynchro- nous clock signals (bufgmux). each bufgmux element, shown in figure 46 , is a 2-to-1 multiplexer. the select line, s, chooses which of the two inputs, i0 or i1, drives the bufgmux?s output signal, o, as described in ta bl e 4 0 . the switching from one clock to the other is glitch-less, and done in such a way that the output high and low times are never shorter than the shortest high or low time of either input clock. the two clock inputs can be asynchronous with regard to each other, and the s input can change at any time, except for a short setup time prior to the rising edge of the presently selected clock (i0 or i1). this setup time is specified as tgsi in ta bl e 1 0 1 , page 140 . violating this setup time requirement possibly results in an undefined runt pulse output. the bufg clock buffer primitive drives a single clock signal onto the clock network and is essentially the same element as a bufgmux, just without the clock select mechanism. similarly, the bufgce primitive creates an enabled clock buffer using the bufgmux select mechanism. the i0 and i1 inputs to an bufgmux element originate from clock input pins, dcms, or double-line interconnect, as shown in figure 46 . as shown in figure 45 , there are 24 bufgmux elements distributed around the four edges of the device. clock signals from the four bufgmux elements at the top edge and the four at the bottom edge are truly glo- bal and connect to all clocking quadrants. the eight left-edge bufgmux elements only connect to the two clock quadrants in the left half of the device. similarly, the eight right-edge bufgmux elements only connect to the right half of the device. bufgmux elements are organized in pairs and share i0 and i1 connections with adjacent bufgmux elements from a common clock switch matrix as shown in figure 46 . for example, the input on i0 of one bufgmux is also a shared input to i1 of the adjacent bufgmux. the clock switch matrix for the left- and right-edge bufg- mux elements receive signals from any of the three follow- ing sources: an lhclk or rhclk pin as appropriate, a double-line interconnect, or a dcm in the xc3s1200e and xc3s1600e devices. table 40: bufgmux select mechanism s input o output 0 i0 input 1 i1 input functional description 60 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r figure 45: spartan-3e internal quadrant-based clock network (electrical connectivity view) 8 8 88 4 8 8 8 8 left s pine top left q ua dr a nt (tl) top right q ua dr a nt (tr) bottom right q ua dr a nt (br) bottom left q ua dr a nt (bl) right s pine horizont a l s pine top s pine bottom s pine 4 ? ? ? ? ? ? ? ? ? ? ? ? d s3 12-2_04_041106 dcm xc 3s 250e (x0y1) xc 3s 500e (x0y1) xc 3s 1200e (x1y 3 ) xc 3s 1600e (x1y 3 ) 4 dcm xc 3s 250e (x0y0) xc 3s 500e (x0y0) xc 3s 1200e (x1y0) xc 3s 1600e (x1y0) 4 4 4 4 dcm xc 3s 100e (x0y1) xc 3s 250e (x1y1) xc 3s 500e (x1y1) xc 3s 1200e (x2y 3 ) xc 3s 1600e (x2y 3 ) 4 dcm xc 3s 100e (x0y0) xc 3s 250e (x1y0) xc 3s 500e (x1y0) xc 3s 1200e (x2y0) xc 3s 1600e (x2y0) x1y10 x1y11 x2y10 x2y11 gclk6 gclk7 gclk10 gclk11 gclk4 gclk5 gclk 8 gclk9 x1y0 x1y1 x2y0 x2y1 gclk14 gclk15 gclk2 gclk 3 gclk12 gclk1 3 gclk0 gclk1 x0y6 x0y7 x0y 8 x0y9 lhclk5 lhclk4 lhclk7 lhclk6 x0y2 x0y 3 x0y4 x0y5 lhclk1 lhclk0 lhclk 3 lhclk2 x 3 y5 x 3 y4 x 3 y 3 x 3 y2 rhclk6 rhclk7 rhclk4 rhclk5 x 3 y9 x 3 y 8 x 3 y7 x 3 y6 rhclk2 rhclk 3 rhclk0 rhclk1 2 2 2 2 2 2 dcm xc 3s 1200e (x0y1) xc 3s 1600e (x0y1) 2 2 dcm xc 3s 1200e (x0y2) xc 3s 1600e (x0y2) dcm xc 3s 1200e (x 3 y2) xc 3s 1600e (x 3 y2) dcm xc 3s 1200e (x 3 y1) xc 3s 1600e (x 3 y1) global clock input s global clock input s left-half clock input s right-half clock input s bufgmux bufgmux h g b a d c f e a c h g b a d c f e b d e gf h p a ir clock line in q ua dr a nt note 4 note 4 note 3 note 3 8 8 8 8 4 4 8 8 8 8 2 2 2 2 2 2 2 2 notes: 1. the diagram presents electrical connectivity. the diagram locations do not necessarily match the physical location on the dev ice, although the coordinate locations shown are correct. 2. number of dcms and locations of these dcm varies for diff erent device densities. the left and right dcms are only in the xc3s1200e and xc3s1600e. the xc3s100e has only two dcms, on e on the top right and one on the bottom right of the die. 3. see figure 47a , which shows how the eight clock lines are multiplexed on the left-hand side of the device. 4. see figure 47b , which shows how the eight clock lines are multiplexed on the right-hand side of the device. 5. for best direct clock inputs to a particular clock buffer, not a dcm, see ta bl e 4 1 . 6. for best direct clock inputs to a particular dcm, not a bufgmux, see ta b l e 3 0 , ta bl e 3 1 , and ta b l e 3 2 . direct pin inputs to a dcm are shown in gray. functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 61 product specification r by contrast, the clock switch matrixes on the top and bottom edges receive signals from any of the five following sources: two gclk pins, two dcm outputs, or one double-line inter- connect. ta bl e 4 1 indicates permissible connections between clock inputs and bufgmux elements. the i0-input provides the best input path to a clock buffer. the i1-input provides the secondary input for the clock multiplexer function. the four bufgmux elements on the top edge are paired together and share inputs from the eight global clock inputs along the top edge. each bufgmux pair connects to four of the eight global clock inputs, as shown in figure 45 . this optionally allows differential inputs to the global clock inputs without wasting a bufgmux element. the connections for the bottom-edge bufgmux elements are similar to the top-edge connections (see figure 46 ). on the left and right edges, only two clock inputs feed each pair of bufgmux elements. ta bl e 4 1 : connections from clock inputs to bufgmux elements and associated quadrant clock quadrant clock line (1) left-half bufgmux top or bottom bufgmux right-half bufgmux location (2) i0 input i1 input location (2) i0 input i1 input location (2) i0 input i1 input h x0y9 lhclk7 lhclk6 x1y10 gclk7 or gclk11 gclk6 or gclk10 x3y9 rhclk3 rhclk2 g x0y8 lhclk6 lhclk7 x1y11 gclk6 or gclk10 gclk7 or gclk11 x3y8 rhclk2 rhclk3 f x0y7 lhclk5 lhclk4 x2y10 gclk5 or gclk9 gclk4 or gclk8 x3y7 rhclk1 rhclk0 e x0y6 lhclk4 lhclk5 x2y11 gclk4 or gclk8 gclk5 or gclk9 x3y6 rhclk0 rhclk1 d x0y5 lhclk3 lhclk2 x1y0 gclk3 or gclk15 gclk2 or gclk14 x3y5 rhclk7 rhclk6 c x0y4 lhclk2 lhclk3 x1y1 gclk2 or gclk14 gclk3 or gclk15 x3y4 rhclk6 rhclk7 b x0y3 lhclk1 lhclk0 x2y0 gclk1 or gclk13 gclk0 or gclk12 x3y3 rhclk5 rhclk4 a x0y2 lhclk0 lhclk1 x2y1 gclk0 or gclk12 gclk1 or gclk13 x3y2 rhclk4 rhclk5 notes: 1. see quadrant clock routing for connectivity details for the eight quadrant clocks. 2. see figure 45 for specific bufgmux locations, and figure 47 for information on how bufgmux elements drive onto a specific clock line within a quadrant. functional description 62 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r quadrant clock routing the clock routing within the fpga is quadrant-based, as shown in figure 45 . each clock quadrant supports eight total clock signals, labeled ?a? through ?h? in ta bl e 4 1 and figure 47 . the clock source for an individual clock line orig- inates either from a global bufgmux element along the top and bottom edges or from a bufgmux element along the associated edge, as shown in figure 47 . the clock lines feed the synchronous resource elements (clbs, iobs, block ram, multipliers, and dcms) within the quadrant. the four quadrants of the device are: ? top right (tr) ? bottom right (br) ? bottom left (bl) ? top left (tl) note that the quadrant clock notation (tr, br, bl, tl) is separate from that used for similar iob placement con- straints. to estimate the quadrant location for a particular i/o, see the footprint diagrams in pinout descriptions (module 4). for exact quadrant locations, use the floorplanning tool. in the qfp packages (tq144 and pq208) the quadrant bor- ders fall in the middle of each side of the package, at a gnd pin. the clock inputs fall on the quadrant boundaries, as indicated in ta b l e 4 2 . in a few cases, a dedicated input is physically in one quad- rant of the device but connects to a different clock quadrant: ? ft256, h16 is in clock quadrant br ? fg320, k2 is in clock quadrant bl ? fg400, l8 is in clock quadrant tl and the i/o at n11 is in clock quadrant bl ? fg484, m2 is in clock quadrant tl and l15 is in clock quadrant br figure 46: clock switch matrix to bufgmux pair connectivity bufgmux lhclk or rhclk inp u t do ub le line dcm o u tp u t * left-/right-half bufgmux clk s witch m a trix s o o s i1 i0 i1 i0 bufgmux top/bottom (global) bufgmux clk s witch m a trix s o o s i1 i0 i1 i0 1 s t gclk pin 2nd gclk pin 1 s t dcm o u tp u t 2nd dcm o u tp u t do ub le line d s3 12-2_16_110706 0 1 0 1 0 1 0 1 *(xc3s1200e and xc3s1600e only) table 42: qfp package clock quadrant locations clock pins quadrant gclk[3:0] br gclk[7:4] tr gclk[11:8] tl gclk[15:12] bl rhclk[3:0] br rhclk[7:4] tr lhclk[3:0] tl lhclk[7:4] bl functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 63 product specification r the outputs of the top or bottom bufgmux elements con- nect to two vertical spines, each comprising four vertical clock lines as shown in figure 45 . at the center of the die, these clock signals connect to the eight-line horizontal clock spine. outputs of the left and right bufgmux elements are routed onto the left or right horizontal spines, each comprising eight horizontal clock lines. each of the eight clock signals in a clock quadrant derives either from a global clock signal or a half clock signal. in other words, there are up to 24 total potential clock inputs to the fpga, eight of which can connect to clocked elements in a single clock quadrant. figure 47 shows how the clock lines in each quadrant are selected from associated bufg- mux sources. for example, if quadrant clock ?a? in the bot- tom left (bl) quadrant originates from bufgmux_x2y1, then the clock signal from bufgmux_x0y2 is unavailable in the bottom left quadrant. however, the top left (tl) quad- rant clock ?a? can still solely use the output from either bufgmux_x2y1 or bufgmu x_x0y2 as the source. to minimize the dynamic power dissipation of the clock net- work, the xilinx development software automatically dis- ables all clock segments not in use. figure 47: clock sources for the eight cloc k lines within a clock quadrant d x1y0 (global) x0y5 (left half) d x1y0 (global) x3y5 (right half) c x1y1 (global) x0y4 (left half) c x1y1 (global) x3y4 (right half) b x2y0 (global) x0y3 (left half) b x2y0 (global) x3y3 (right half) x2y1 (global) a x0y2 (left half) x2y1 (global) a x3y2 (right half) bufgmux output clock line e x2y11 (global) x0y6 (left half) e x2y11 (global) x3y6 (right half) f x2y10 (global) x0y7 (left half) f x2y10 (global) x3y7 (right half) g x1y11 (global) x0y8 (left half) g x1y11 (global) x3y8 (right half) h x1y10 (global) x0y9 (left half) h x1y10 (global) x3y9 (right half) bufgmux output DS312-2_17_103105 a. left (tl and bl quadrants) half of die b. ri g ht (tr and br quadrants) half of die clock line functional description 64 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r interconnect for additional information, refer to the using interconnect chapter in ug331 . interconnect is the programmable network of signal path- ways between the inputs and outputs of functional elements within the fpga, such as iobs, clbs, dcms, and block ram. overview interconnect, also called routing, is segmented for optimal connectivity. functionally, interconnect resources are identi- cal to that of the spartan-3 architecture. there are four kinds of interconnects: long lines, hex lines, double lines, and direct lines. the xilinx pl ace and route (par) software exploits the rich interconnect array to deliver optimal system performance and the fastest compile times. switch matrix the switch matrix connects to the different kinds of intercon- nects across the device. an interconnect tile, shown in figure 48 , is defined as a single switch matrix connected to a functional element, such as a clb, iob, or dcm. if a func- tional element spans across multiple switch matrices such as the block ram or multipliers, then an interconnect tile is defined by the number of switch matrices connected to that functional element. a spartan-3e device can be repre- sented as an array of interconnect tiles where interconnect resources are for the channel between any two adjacent interconnect tile rows or columns as shown in figure 49 . figure 48: four types of interconnect tiles (clbs, iobs, dcms, and block ram/multiplier) switch matrix switch matrix switch matrix switch matrix switch matrix clb 1 8 k b block ram mult 1 8 x 1 8 switch matrix iob switch matrix dcm DS312_0 8 _020905 functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 65 product specification r figure 49: array of interconnect tiles in spartan-3e fpga switch matrix iob switch matrix iob switch matrix iob switch matrix switch matrix switch matrix iob switch matrix clb switch matrix clb switch matrix switch matrix switch matrix iob switch matrix clb switch matrix clb switch matrix switch matrix switch matrix iob switch matrix clb switch matrix clb switch matrix switch matrix switch matrix iob switch matrix clb switch matrix clb iob clb clb clb clb switch matrix switch matrix DS312_09_020905 horizontal and vertical long lines (horizontal channel shown as an example) horizontal and vertical hex lines (horizontal channel shown as an example) horizontal and vertical double lines (horizontal channel shown as an example) figure 50: interconnect types between two adjacent interconnect tiles ? ? ? clb clb ? ? ? clb clb ? ? ? clb clb 66 666 ? ? ? clb clb ? ? ? clb clb DS312-2_10_022305 24 clb clb clb clb clb clb clb 8 DS312-2_11_020905 clb 8 clb clb DS312-2_15_022305 functional description 66 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r the four types of general-purpose interconnect available in each channel, shown in figure 50 , are described below. long lines each set of 24 long line signals spans the die both horizon- tally and vertically and connects to one out of every six inter- connect tiles. at any tile, fo ur of the long lines drive or receive signals from a switch matrix. because of their low capacitance, these lines are well-suited for carrying high-frequency signals with minimal loading effects (e.g. skew). if all global clock lines are already committed and additional clock signals remain to be assigned, long lines serve as a good alternative. hex lines each set of eight hex lines are connected to one out of every three tiles, both horizontally and vertically. thirty-two hex lines are available between any given interconnect tile. hex lines are only driven from one end of the route. double lines each set of eight double lines are connected to every other tile, both horizontally and vert ically. in all four directions. thirty-two double lines available between any given inter- connect tile. double lines are more connections and more flexibility, compared to long line and hex lines. direct connections direct connect lines route signals to neighboring tiles: verti- cally, horizontally, and diagonally. these lines most often drive a signal from a "source" tile to a double, hex, or long line and conversely from the longer interconnect back to a direct line accessing a "destination" tile. global controls (startup_spartan3e) in addition to the general-purpose interconnect, spartan-3e fpgas have two global logic control signals, as described in ta b l e 4 3 . these signals are available to the fpga appli- cation via the startup_spartan3e primitive. the global set/reset (gsr) signal replaces the global reset signal included in many asic-style designs. use the gsr control instead of a separate global reset signal in the design to free up clb inputs, resulting in a smaller, more efficient design. similarly, the gsr signal is asserted auto- matically during the fpga configuration process, guaran- teeing that the fpga starts-up in a known state. the startup_spartan3e primitive also includes two other signals used specifically during configuration. the mbt signals are for dynamically loading multiple con- figuration images using multiboot option , page 93 . the clk input is an alternate clock for configuration start-up , page 107 . direct connections figure 50: interconnect types between two adjacent interconnect tiles (continued) clb clb clb clb clb clb clb clb clb DS312-2_12_020905 table 43: spartan-3e global logic control signals global control input description gsr global set/reset: when high, asynchronously places all registers and flip-flops in their initial state (see initialization , page 32 ). asserted automatically during the fpga configuration process (see start-up , page 107 ). gts global three-state: when high, asynchronously forces all i/o pins to a high-impedance state (hi-z, three-state). functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 67 product specification r configuration for additional information on configuration, refer to ug332 : spartan-3 generation configuration user guide . differences from spartan-3 fpgas in general, spartan-3e fpga configuration modes are a superset to those available in spartan-3 fpgas. two new modes added in spartan-3e fpgas provide a glue-less configuration interface to i ndustry-standard parallel nor flash and spi serial flash memories. configuration process the function of a spartan-3e fpga is defined by loading application-specific configuration data into the fpga?s internal, reprogrammable cmos configuration latches (ccls), similar to the way a microprocessor?s function is defined by its application program. for fpgas, this configu- ration process uses a subset of the device pins, some of which are dedicated to configuration; other pins are merely borrowed and returned to the application as general-pur- pose user i/os after configuration completes. spartan-3e fpgas offer several configuration options to minimize the impact of configuration on the overall system design. in some configuration modes, the fpga generates a clock and loads itself from an external memory source, either serially or via a byte-wide data path. alternatively, an external host such as a microprocessor downloads the fpga?s configuration data using a simple synchronous serial interface or via a byte-wide peripheral-style interface. furthermore, multiple-fpga designs share a single config- uration memory source, creating a structure called a daisy chain. three fpga pins?m2, m1, and m0?select the desired configuration mode. the mode pin settings appear in ta b l e 4 4 . the mode pin values are sampled during the start of configuration when the fpga?s init_b output goes high. after the fpga completes configuration, the mode pins are available as user i/os. ta bl e 4 4 : spartan-3e configuration mode options and pin settings master serial spi bpi slave parallel slave serial jtag m[2:0] mode pin settings <0:0:0> <0:0:1> <0:1:0>=up <0:1:1>=down <1:1:0> <1:1:1> <1:0:1> data width serial serial byte-wide byte-wide serial serial configuration memory source xilinx platform flash industry-standard spi serial flash industry-standard parallel nor flash or xilinx parallel platform flash any source via microcontroller, cpu, xilinx parallel platform flash , etc. any source via microcontroller, cpu, xilinx platform flash , etc. any source via microcontroller, cpu, s ystem a ce ? c f , etc. clock source internal oscillator internal oscillator internal oscillator external clock on cclk pin external clock on cclk pin external clock on tck pin total i/o pins borrowed during configuration 8 13 46 21 8 0 configuration mode for downstream daisy-chained fpgas slave serial slave serial slave parallel slave parallel or memory mapped slave serial jtag stand-alone fpga applications (no external download host) possible using xcfxxp platform flash, which optionally generates cclk possible using xcfxxp platform flash, which optionally generates cclk uses low-cost, industry-standard flash supports optional multiboot, multi-configuration mode functional description 68 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r configuration bitstream image sizes a specific spartan-3e part type always requires a constant number of configuration bits, regardless of design complex- ity, as shown in ta bl e 4 5 . the configuration file size for a multiple-fpga daisy-chain design roughly equals the sum of the individual file sizes. pin behavior during configuration for additional informat ion, refer to the ? configuration pins and behavior during configuration ? chapter in ug332 . ta b l e 4 6 shows how various pins behave during the fpga configuration process. the actual behavior depends on the values applied to the m2, m1, and m0 mode select pins and the hswap pin. the mode select pins determine which of the i/o pins are borrowed during configuration and how they function. in jtag configuration mode, no user-i/o pins are borrowed for configuration. all user-i/o pins, input-only pins, and dual-purpose pins that are not actively involved in the currently-select configuration mode are high impedance (floating, three-stated, hi-z) dur- ing the configuration process. these pins are indicated in ta b l e 4 6 as gray shaded table entries or cells. the hswap input controls whether all user-i/o pins, input-only pins, and dual-purpose pins have a pull-up resis- tor to the supply rail or not. when hswap is low, each pin has an internal pull-up resistor that is active throughout con- figuration. after configuration, pull-up and pull-down resis- tors are available in the fpga application as described in pull-up and pull-down resistors . the yellow-shaded table entries or cells represent pins where the pull-up resistor is always enabled during configu- ration, regardless of the hswap input. the post-configura- tion behavior of these pins is defined by bitstream generator options as defined in ta bl e 6 9 . ta bl e 4 5 : number of bits to program a spartan-3e fpga (uncompressed bitstreams) spartan-3e fpga number of configuration bits xc3s100e 581,344 xc3s250e 1,353,728 xc3s500e 2,270,208 xc3s1200e 3,841,184 xc3s1600e 5,969,696 ta bl e 4 6 : pin behavior during configuration pin name master serial spi (serial flash) bpi (parallel nor flash) jtag slave parallel slave serial i/o bank (3) io* (user-i/o) ip* (input-only) - tdi tdi tdi tdi tdi tdi tdi v ccaux tms tms tms tms tms tms tms v ccaux tck tck tck tck tck tck tck v ccaux tdo tdo tdo tdo tdo tdo tdo v ccaux prog_b prog_b prog_b prog_b prog_b prog_b prog_b v ccaux done done done done done done done v ccaux hswap hswap hswap hswap hswap hswap hswap 0 m2 0 0 0 1 1 1 2 m1 0 0 1 0 1 1 2 m0 0 1 0 = up 1 = down 1 0 1 2 cclk cclk (i/o) cclk (i/o) cclk (i/o) cclk (i) cclk (i) 2 init_b init_b init_b init_b init_b init_b 2 cso_b cso_b cso_b cso_b 2 dout/busy dout dout busy busy dout 2 mosi/csi_b mosi csi_b csi_b 2 d7 d7 d7 2 d6 d6 d6 2 d5 d5 d5 2 d4 d4 d4 2 d3 d3 d3 2 d2 d2 d2 2 functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 69 product specification r the hswap pin itself has an pull-up resistor enabled during configuration. however, the vcco_0 supply voltage must be applied before the pull-up resistor becomes active. if the vcco_0 supply ramps after the vcco_2 power supply, do not let hswap float; tie hswap to the desired logic level externally. spartan-3e fpgas have only six dedicated configuration pins, including the done and prog_b pins, and the four d1 d1 d1 2 d0/din din din d0 d0 din 2 rdwr_b rdwr_b rdwr_b 2 a23 a23 2 a22 a22 2 a21 a21 2 a20 a20 2 a19/vs2 vs2 a19 2 a18/vs1 vs1 a18 2 a17/vs0 vs0 a17 2 a16 a16 1 a15 a15 1 a14 a14 1 a13 a13 1 a12 a12 1 a11 a11 1 a10 a10 1 a9 a9 1 a8 a8 1 a7 a7 1 a6 a6 1 a5 a5 1 a4 a4 1 a3 a3 1 a2 a2 1 a1 a1 1 a0 a0 1 ldc0 ldc0 1 ldc1 ldc1 1 ldc2 ldc2 1 hdc hdc 1 notes: 1. gray shaded cells represent pins that are in a high-impedance state (hi-z, floating) during co nfiguration. these pins have an optional internal pull-up resistor to their respective v cco supply pin that is active throughout c onfiguration if the hswap input is low. 2. yellow shaded cells represent pins with an internal pull-up resi stor to its respective voltage supply rail that is active dur ing configuration, regardless of the hswap pin. 3. note that dual-purpose outputs are supplied by v cco , and configuration inputs are supplied by v ccaux . ta bl e 4 6 : pin behavior during configuration (continued) pin name master serial spi (serial flash) bpi (parallel nor flash) jtag slave parallel slave serial i/o bank (3) ta bl e 4 7 : default i/o standard setting duri ng configuration (vcco_2 = 2.5v) pin(s) i/o standard output drive slew rate all, including cclk lvcmos25 8 ma slow functional description 70 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r jtag boundary-scan pins: tdi, tdo, tms, and tck. all other configuration pins are dual-purpose i/o pins and are available to the fpga application after the done pin goes high. see start-up for additional information. ta bl e 4 7 shows the default i/o standard setting for the vari- ous configuration pins during the configuration process. the configuration interface is designed primarily for 2.5v opera- tion when the vcco_2 (and vcco_1 in bpi mode) con- nects to 2.5v. the configuration pins also operate at other voltages by set- ting vcco_2 (and vcco_1 in bpi mode) to either 3.3v or 1.8v. the change on the v cco supply also changes the i/o characteristics, including the effective iostandard. for example, with v cco = 3.3v, the output characteristics will be similar to those of lvcmos33, and the current when driving high, i oh , increases to approximately 12 to 16 ma, while the current when driving low, i ol , remains 8 ma. at v cco = 1.8v, the output characteristics will be similar to those of lvcmos18, and the current when driving high, i oh , decreases slightly to approximately 6 to 8 ma. again, the current when driving low, i ol , remains 8 ma. the out- put voltages are determined by the v cco level, lvcmos18 for 1.8v, lvcmos25 for 2.5v, and lvcmos33 for 3.3v. for more details see ug332 . cclk design considerations for additional informat ion, refer to the ? configuration pins and behavior during configuration ? chapter in ug332 . the fpga?s configuration process is controlled by the cclk configuration clock. consequently, signal integrity of cclk is important to guarantee successful configuration. poor cclk signal integrity caused by ringing or reflections might cause double-clocking, causing the configuration pro- cess to fail. although the cclk frequency is relatively low, spartan-3e fpga output edge rates are fast. therefore, careful atten- tion must be paid to the cclk signal integrity on the printed circuit board. signal integrity simulation with ibis is recom- mended. for all configuration modes except jtag, the sig- nal integrity must be considered at every cclk trace destination, including the fpga?s cclk pin. this analysis is especially important when the fpga re-uses the cclk pin as a user-i/o after configuration. in these cases, there might be unrelated devices attached to cclk, which add additional trace length and signal destina- tions. in the master serial, spi, and bpi configuration modes, the fpga drives the cclk pin and cclk should be treated as a full bidirectional i/o pin for signal integrity analysis. in bpi mode, cclk is only used in multi-fpga daisy-chains. the best signal integrity is ensured by following these basic pcb guidelines: ? route the cclk signal as a 50 controlled-impedance transmission line. ? route the cclk signal without any branching. do not use a ?star? topology. ? keep stubs, if required, shorter than 10 mm (0.4 inches). ? terminate the end of the cclk transmission line. design considerations fo r the hswap, m[2:0], and vs[2:0] pins for additional information, refer to the ? configuration pins and behavior during configuration ? chapter in ug332 . unlike previous spartan fpga families, nearly all of the spartan-3e dual-purpose configuration pins are available as full-featured user i/o pins after successful configuration, when the done output goes high. the hswap pin, the mode select pins (m[2:0]), and the variant-select pins (vs[2:0]) must have valid and stable logic values at the start of configuration. vs[2:0] are only used in the spi configuration mode. the levels on the m[2:0] pins and vs[2:0] pins are sampled when the init_b pin returns high. see figure 77 for a timing example. the hswap pin defines whether fpga user i/o pins have a pull-up resistor connected to their associated v cco sup- ply pin during configuration or not, as shown ta b l e 4 8 . hswap must be valid at the start of configuration and remain constant throughout the configuration process. table 48: hswap behavior hswap value description 0 pull-up resistors connect to the associated v cco supply for all user-i/o or dual-purpose i/o pins during configuration. pull-up resistors are active until configuration completes. 1 pull-up resistors disabled during configuration. all user-i/o or dual-purpose i/o pins are in a high-impedance state. functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 71 product specification r the configuration section provides detailed schematics for each configuration mode. the schematics indicate the required logic values for hswap, m[2:0], and vs[2:0] but do not specify how the applicatio n provides the logic low or high value. the hswap, m[2:0], and vs[2:0] pins can be either dedicated or reused by the fpga application. dedicating the hswap, m[2:0], and vs[2:0] pins if the hswap, m[2:0], and vs[2:0] pins are not required by the fpga design after configuration, simply connect these pins directly to the v cco or gnd supply rail shown in the appropriate configuration schematic. reusing hswap, m[2:0], and vs[2:0] after config- uration to reuse the hswap, m[2:0], and vs[2:0] pin after configu- ration, use pull-up or pull-down resistors to define the logic values shown in the appropriate configuration schematic. the logic level on hswap dictates how to define the logic levels on m[2:0] and vs[2:0], as shown in ta b l e 4 9 . if the application requires hswap to be high, the hswap pin is pulled high using an external 3.3 to 4.7 k resistor to vcco_0. if the application requires hswap to be low dur- ing configuration, then hswap is either connected to gnd or pulled low using an appropriately sized external pull-down resistor to gnd. when hswap is low, its pin has an internal pull-up resistor to vcco_0. the external pull-down resistor must be strong enough to define a logic low on hswap for the i/o standard used during configura- tion. for 2.5v or 3.3v i/o, the pull-down resistor is 560 or lower. for 1.8v i/o, the pull-down resistor is 1.1 k or lower. once hswap is defined, use ta bl e 4 9 to define the logic values for m[2:0] and vs[2:0]. use the weakest external pull-up or pull-down resistor value allowed by the application. the resistor must be strong enough to define a logic low or high during configuration. however, when driving the hswap, m[2:0], or vs[2:0] pins after configuration, the output driver must be strong enough to overcome the pull-up or pull-down resistor value and gen- erate the appropriate logic levels. for example, to overcome a 560 pull-down resistor, a 3.3v fpga i/o pin must use a 6 ma or stronger driver. ta bl e 4 9 : pull-up or pull-down values for hswap, m[2:0], and vs[2:0] hswap value i/o pull-up resistors during configuration required resistor value to define logic level on hswap, m[2:0], or vs[2:0] high low 0 enabled pulled high via an internal pull-up resistor to the associated v cco supply. no external pull-up resistor is necessary. pulled low using an appropriately sized pull-down resistor to gnd. for a 2.5v or 3.3v interface: r < 560 . for a 1.8v interface: r < 1.1 k . 1 disabled pulled high using a 3.3 to 4.7 k resistor to the associated v cco supply. pulled low using a 3.3 to 4.7 k resistor to gnd. functional description 72 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r master serial mode for additional information, refer to the master serial mode chapter in ug332 . in master serial mode (m[2:0] = <0:0:0>), the spartan-3e fpga configures itself from an attached xilinx platform flash prom, as illustrated in figure 51 . the fpga sup- plies the cclk output clock from its internal oscillator to the attached platform flash prom. in response, the platform flash prom supplies bit-serial data to the fpga?s din input, and the fpga accepts this data on each rising cclk edge. all mode select pins, m[2:0], must be low when sampled, when the fpga?s init_b output goes high. after configura- tion, when the fpga?s done output goes high, the mode select pins are available as full-featured user-i/o pins. similarly, the fpga?s hswap pin must be low to enable pull-up resistors on all user-i/o pins during configu- ration or high to disable the pull-up resistors. the hswap control must remain at a co nstant logic level throughout fpga configuration. after configuration, when the fpga?s done output goes high, the hswap pin is available as full-featured user-i/o pin and is powered by the vcco_0 supply. the fpga's dout pin is used in daisy-chain applications, described later. in a single-fpga application, the fpga?s dout pin is not used but is actively driving during the con- figuration process. figure 51: master serial mode using platform flash prom tdi tdo tm s tck vccint vccaux +2.5v init_b vcco_2 cclk din prog_b done gnd +1.2v d0 cf vccint clk h s wap vcco_0 p vcco_0 +2.5v jtag prog_b recommend open-drain driver tdi tm s tck tdo xcfxx s = + 3 . 3 v xcfxxp = +1. 8 v ce m2 m1 ?0? ?0? m0 serial ma s ter mode ?0? dout oe/re s et v v gnd tdi tm s tck tdo vccj +2.5v vcco v ceo platform fla s h xcfxx 33 0 +2.5v 4.7k 4.7k d s3 12-2_44_0 8 2009 spartan- 3 e fpga p functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 73 product specification r ta bl e 5 0 : serial master mode connections pin name fpga direction description during configuration after configuration hswap input user i/o pull-up control . when low during configuration, enables pull-up resistors in all i/o pins to respective i/o bank v cco input. 0: pull-ups during configuration 1: no pull-ups drive at valid logic level throughout configuration. user i/o m[2:0] input mode select . selects the fpga configuration mode. see design considerations for the hswap, m[2:0], and vs[2:0] pins . m2 = 0, m1 = 0, m0 = 0. sampled when init_b goes high. user i/o din input serial data input . receives serial data from prom?s d0 output. user i/o cclk output configuration clock . generated by fpga internal oscillator. frequency controlled by configrate bitstream generator option. if cclk pcb trace is long or has multiple connections, terminate this output to maintain signal integrity. see cclk design considerations . drives prom?s clk clock input. user i/o dout output serial data output . actively drives. not used in single-fpga designs. in a daisy-chain configuration, this pin connects to din input of the next fpga in the chain. user i/o init_b open-drain bidirectional i/o initialization indicator . active low. goes low at start of configuration during initialization memory clearing process. released at end of memory clearing, when mode select pins are sampled. requires external 4.7 k pull-up resistor to vcco_2. connects to prom?s oe/reset input. fpga clears prom?s address counter at start of configuration, enables outputs during configuration. prom also holds fpga in initialization state until prom reaches power-on reset (por) state. if crc error detected during configuration, fpga drives init_b low. user i/o. if unused in the application, drive init_b high. done open-drain bidirectional i/o fpga configuration done . low during configuration. goes high when fpga successfully complete s configuration. requires external 330 pull-up resistor to 2.5v. connects to prom?s chip-enable (ce) input. enables prom during configuration. disables prom after configuration. pulled high via external pull-up. when high, indicates that the fpga successfully configured. prog_b input program fpga . active low. when asserted low for 500 ns or longer, forces the fpga to restart its configuration process by clearing configuration memory and resetting the done and init_b pins once prog_b returns high. recommend external 4.7 k pull-up resistor to 2.5v. internal pull-up value may be weaker (see ta b l e 7 8 ). if driving externally with a 3.3v output, use an open-drain or open-collector driver or use a current limiting series resistor. must be high during configuration to allow configuration to start. connects to prom?s cf pin, allowing jtag prom programming algorithm to reprogram the fpga. drive prog_b low and release to reprogram fpga. p functional description 74 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r voltage compatibility the prom?s v ccint supply must be either 3.3v for the serial xcfxxs platform flash proms or 1.8v for the serial/parallel xcfxxp proms. the fpga?s vcco_2 supply input and the platform flash prom?s v cco supply input must be the same volt- age, ideally +2.5v. both devices also support 1.8v and 3.3v interfaces but the fpga?s prog_b and done pins require special attention as they are powered by the fpga?s v ccaux supply, nominally 2.5v. see application note xapp453 : the 3.3v configuration of spartan-3 fpgas for additional information. supported platform flash proms ta bl e 5 1 shows the smallest available platform flash prom to program one spartan-3e fpga. a multiple-fpga daisy-chain application requires a platform flash prom large enough to contain the sum of the various fpga file sizes. the xc3s1600e requires an 8 mbit prom. two solutions are possible: either a single 8 mbit xcf08p parallel/serial prom or two 4 mbit xcf04s serial proms cascaded. the two xcf04s proms use a 3.3v v ccint supply while the xcf08p requires a 1.8v v ccint supply. if the board does not already have a 1.8v supply available, the two cascaded xcf04s prom solution is recommended. cclk frequency in master serial mode, the fp ga?s internal oscillator gener- ates the configuration clock frequency. the fpga provides this clock on its cclk output pin, driving the prom?s clk input pin. the fpga starts configuration at its lowest fre- quency and increases its frequency for the remainder of the configuration process if so specified in the configuration bit- stream. the maximum frequency is specified using the configrate bitstream generator option. ta bl e 5 2 shows the maximum configrate settings, approximately equal to mhz, for various platform flash devices and i/o voltages. for the serial xcfxxs proms, the maximum frequency also depends on the interface voltage. ta bl e 5 1 : number of bits to program a spartan-3e fpga and smallest platform flash prom spartan-3e fpga number of configuration bits smallest available platform flash xc3s100e 581,344 xcf01s xc3s250e 1,353,728 xcf02s xc3s500e 2,270,208 xcf04s xc3s1200e 3,841,184 xcf04s xc3s1600e 5,969,696 xcf08p or 2 x xcf04s v table 52: maximum configrate settings for platform flash platform flash part number i/o voltage (vcco_2, v cco ) maximum configrate setting xcf01s xcf02s xcf04s 3.3v or 2.5v 25 1.8v 12 xcf08p xcf16p xcf32p 3.3v, 2.5v, or 1.8v 25 functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 75 product specification r daisy-chaining if the application requires multiple fpgas with different con- figurations, then configure the fpgas using a daisy chain, as shown in figure 52 . use master serial mode (m[2:0] = <0:0:0>) for the fpga connected to the platform flash prom and slave serial mode (m[2:0] = <1:1:1>) for all other fpgas in the daisy-chain. after the master fpga?the fpga on the left in the diagram?finishes load- ing its configuration data from the platform flash, the mas- ter device supplies data using its dout output pin to the next device in the daisy-chain, on the falling cclk edge. jtag interface both the spartan-3e fpga and the platform flash prom have a four-wire ieee 1149.1/1532 jtag port. both devices share the tck clock input and the tms mode select input. the devices may connect in either order on the jtag chain with the tdo output of one device feeding the tdi input of the following device in the chain. the tdo output of the last device in the jtag chain drives the jtag connector. the jtag interface on spartan-3e fpgas is powered by the 2.5v v ccaux supply. consequently, the prom?s v ccj supply input must also be 2.5v. to create a 3.3v jtag inter- face, please refer to application note xapp453 : the 3.3v configuration of spartan-3 fpgas for additional informa- tion. in-system programming support both the fpga and the platform flash prom are in-system programmable via the jtag chain. download support is provided by the xilinx impact programming software and the associated xilinx parallel cable iv or platform cable usb programming cables. storing additional user data in platform flash after configuration, the fpga application can continue to use the master serial interface pins to communicate with the platform flash prom. if desired, use a larger platform flash prom to hold additional non-volatile application data, such as microblaze processor code, or other user data such as serial numbers and ethernet mac ids. the fpga first configures from platform flash prom. then using fpga logic after configuration, the fpga copies microblaze code from platform flash into external ddr sdram for code execution. see xapp694 : reading user data from configuration proms and xapp482 : microblaze platform flash/prom boot loader and user data storage for specific details on how to implement such an interface. spi serial flash mode for additional information, refer to the ? master spi mode? chapter in ug332 . in spi serial flash mode ( m[2:0] = <0:0:1> ), the spartan-3e fpga configures itself from an attached industry-standard spi serial flash prom, as illustrated in figure 53 and figure 54 . the fpga supplies the cclk output clock from its internal oscillator to the clock input of the attached spi flash prom. figure 52: daisy-chaining from master serial mode +2.5v tdi tdo tm s tck vccint vccaux +2.5v init_b vcco_2 cclk din prog_b done gnd +1.2v d0 cf vccint clk h s wap vcco_0 p tdi tdo tm s tck vccint vccaux din dout vcco_2 init_b prog_b done gnd +1.2v m2 m1 ?1? ?1? m0 h s wap vcco_0 p +2.5v ?1? vcco_0 slave serial mode spartan- 3 e fpga spartan- 3 e fpga +2.5v jtag cclk init_b done prog_b tck tm s prog_b recommend open-drain driver vcco_0 tdi tm s tck tdo xcfxx s = + 3 . 3 v xcfxxp = +1. 8 v ce m2 m1 ?0? ?0? m0 serial ma s ter mode ?0? dout dout cclk oe/re s et v v gnd tdi tm s tck tdo vccj +2.5v vcco v ceo platform fla s h xcfxx 4.7k 4.7k 33 0 v d s3 12-2_45_0 8 2009 functional description 76 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r although spi is a standard four-wire interface, various available spi flash proms use different command proto- cols. the fpga?s variant select pins, vs[2:0], define how the fpga communicates with the spi flash, including which spi flash command the fpga issues to start the read operation and the number of dummy bytes inserted before the fpga expects to receive valid data from the spi flash. ta b l e 5 3 shows the available spi flash proms expected to operate with spartan-3e fpgas. other com- patible devices might work but have not been tested for suit- ability with spartan-3e fpgas. all other vs[2:0] values are reserved for future use. consult the data sheet for the desired spi flash device to determine its suitability. the basic timing requirements and waveforms are provided in serial peripheral interface (spi) configuration timing in module 3. figure 53 shows the general connection diagram for those spi flash proms that support the 0x03 read command or the 0x0b fast read commands. figure 54 shows the connection diagram for atmel dataflash serial proms, which also use an spi-based pro- tocol. ?b?-series dataflash devices are limited to fpga applications operating over the commercial temperature range. industrial temperature range applications must use ?c?- or ?d?-series dataflash devices, which have a shorter dataflash select setup time, because of the faster fpga cclk frequency at cold temperatures. figure 57, page 84 demonstrates how to configure multiple fpgas with different configurations, all stored in a single spi flash. the diagram uses standard spi flash memories but the same general technique applies for atmel dataflash. figure 53: spi flash prom interface for proms supporting read (0x03) and fast_read (0x0b) commands d s3 12-2_46_0 8 2009 tdi tdo tm s tck vccint vccaux +2.5v c s o_b vcco_2 init_b din mo s i prog_b done gnd +1.2v data_in s elect vcc data_out clock gnd h s wap vcco_0 cclk vcco_0 spartan- 3 e fpga +2.5v jtag spi serial fla s h prog_b recommend open-drain driver tdi tm s tck tdo + 3 . 3 v + 3 . 3 v hold ?1? m2 m1 ?0? ?0? m0 spi mode ?1? v s 2 v s 1 ?1? v s 0 variant select ?1? dout wr_protect 4.7k + 3 . 3 v 4.7k +2.5v 4.7k 33 0 p s w i p s functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 77 product specification r figure 54: atmel spi-based dataflash configuration interface d s3 12-2_50 a _0 8 2009 tdi tdo tm s tck vccint vccaux +2.5v c s o_b vcco_2 init_b din mo s i prog_b done gnd s i c s vcc s o s ck gnd h s wap vcco_0 p cclk vcco_0 spartan- 3 e fpga +2.5v jtag atmel at45db datafla s h prog_b recommend open-drain driver tdi tm s tck tdo + 3 . 3 v + 3 . 3 v re s et ?1? m2 m1 ?0? ?0? m0 spi mode ?1? v s 2 v s 1 ?1? v s 0 variant select ?0? dout wp w p i 4.7k + 3 . 3 v 4.7 k +2.5v 4.7k 33 0 ?1? rdy/bu s y +1.2v power-on monitor + 3 . 3 v power-on monitor + 3 . 3 v or power-on monitor is only required if +3.3v (vcco_2) supply is the last supply in power-on sequence, after vccint and vccaux. must delay fpga configuration for > 20 ms after spi dataflash reaches its minimum vcc. force fpga init_b input or prog_b input low with an open-drain or open- collector driver. init_b prog_b functional description 78 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r ta bl e 5 3 : variant select codes for vari ous spi serial flash proms vs2 vs1 vs0 spi read command dummy bytes spi serial flash vendor spi flash family impact programming support 1 1 1 fast read (0x0b) (see figure 53 ) 1 stmicroelectronics (st) m25pxx m25pexx/m45pexx ye s atmel at45db ?d?-series data flas h ye s at 2 6 / at 2 5 (1) intel s33 spansion (amd , fujitsu) s25flxxxa winbond (nexflash) nx25 / w25 macronix mx25lxxxx silicon storage technology (sst) sst25lfxxxa sst25vfxxxa programmable microelectronics corp. (pmc) pm25lvxxx amic technology a25l eon silicon solution, inc. en25 1 0 1 read (0x03) (see figure 53 ) 0 stmicroelectronics (st) m25px x m25pexx/m45pexx ye s spansion (amd, fujitsu) s25flxxxa winbond (nexflash) nx25 / w25 macronix mx25lxxxx silicon storage technology (sst) sst25lfxxxa sst25vfxxxa sst25vfxxx programmable microelectronics corp. (pmc) pm25lvxxx 1 1 0 read array (0xe8) (see figure 54 ) 4 atmel corporation at45db dataflash (use only ? c? or ?d? series for industrial temperature range ) ye s others reserved notes: 1. see impact documentation for specific device support. functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 79 product specification r ta b l e 5 4 shows the connections between the spi flash prom and the fpga?s spi configuration interface. each spi flash prom vendor uses slightly different signal nam- ing. the spi flash prom?s write protect and hold controls are not used by the fpga during configuration. however, the hold pin must be high during the configuration pro- cess. the prom?s write protect input must be high in order to write or program the flash memory. the mode select pins, m[2:0], and the variant select pins, vs[2:0] are sampled when the fpga?s init_b output goes high and must be at defined logic levels during this time. after configuration, when the fpga?s done output goes high, these pins are all available as full-featured user-i/o pins. similarly, the fpga?s hswap pin must be low to enable pull-up resistors on all user-i/o pins or high to dis- able the pull-up resistors. the hswap control must remain at a constant logic level throughout fpga configuration. after configuration, when the fpga?s done output goes high, the hswap pin is available as full-featured user-i/o pin and is powered by the vcco_0 supply. in a single-fpga application, the fpga?s dout pin is not used but is actively driving during the configuration process. w ta bl e 5 4 : example spi flash prom connections and pin naming spi flash pin fpga connection stmicro nexflash silicon storage technology atmel dataflash data_in mosi d di si si data_out din q do so so select cso_b s cs ce# cs clock cclk c clk sck sck wr_protect not required for fpga configuration. must be high to program spi flash. optional connection to fpga user i/o after configuration. w wp wp# wp hold (see figure 53 ) not required for fpga configuration but must be high during configuration. optional connection to fpga user i/o after configuration. not applicable to atmel dataflash. hold hold hold# n/a reset (see figure 54 ) only applicable to atmel dataflash. not required for fpga configuration but must be high during configuration. optional connection to fpga user i/o after configuration. do not connect to fpga?s prog_b as this will prevent direct programming of the dataflash. n/a n/a n/a reset rdy/busy (see figure 54 ) only applicable to atmel dataflash and only available on certain packages. not required for fpga configuration. output from dataflash prom. optional connection to fpga user i/o after configuration. n/a n/a n/a rdy/busy w p functional description 80 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r ta bl e 5 5 : serial peripheral interface (spi) connections pin name fpga direction description during configuration after configuration hswap input user i/o pull-up control . when low during configuration, enables pull-up resistors in all i/o pins to respective i/o bank v cco input. 0: pull-ups during configuration 1: no pull-ups drive at valid logic level throughout configuration. user i/o m[2:0] input mode select . selects the fpga configuration mode. see design considerations for the hswap, m[2:0], and vs[2:0] pins . m2=0, m1=0, m0=1. sampled when init_b goes high. user i/o vs[2:0] input variant select . instructs the fpga how to communicate with the attached spi flash prom. see design considerations for the hswap, m[2:0], and vs[2:0] pins . must be at the logic levels shown in ta bl e 5 3 . sampled when init_b goes high. user i/o mosi output serial data output . fpga sends spi flash memory read commands and starting address to the prom?s serial data input. user i/o din input serial data input . fpga receives serial data from prom?s serial data output. user i/o cso_b output chip select output . active low. connects to the spi flash prom?s chip-select input. if hswap = 1, connect this signal to a 4.7 k pull-up resistor to 3.3v. drive cso_b high after configuration to disable the spi flash and reclaim the mosi, din, and cclk pins. optionally, re-use this pin and mosi, din, and cclk to continue communicating with spi flash. cclk output configuration clock . generated by fpga internal oscillator. frequency controlled by configrate bitstream generator option. if cclk pcb trace is long or has multiple connections, terminate this output to maintain signal integrity. see cclk design considerations . drives prom?s clock input. user i/o dout output serial data output . actively drives. not used in single-fpga designs. in a daisy-chain configuration, this pin connects to din input of the next fpga in the chain. user i/o init_b open-drain bidirectional i/o initialization indicator . active low. goes low at start of configuration during initialization memory clearing process. released at end of memory clearing, when mode select pins are sampled. in daisy-chain applications, this signal requires an external 4.7 k pull-up resistor to vcco_2. active during configuration. if spi flash prom requires > 2 ms to awake after powering on, hold init_b low until prom is ready. if crc error detected during configuration, fpga drives init_b low. user i/o. if unused in the application, drive init_b high. p s functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 81 product specification r voltage compatibility available spi flash proms use a single 3.3v supply volt- age. all of the fpga?s spi flash interface signals are within i/o bank 2. consequently, the fpga?s vcco_2 supply volt- age must also be 3.3v to match the spi flash prom. power-on precautions if 3.3v supply is last in sequence spartan-3e fpgas have a built-in power-on reset (por) circuit, as shown in figure 66 . the fpga waits for its three power supplies ? v ccint , v ccaux , and v cco to i/o bank 2 (vcco_2) ? to reach their respective power-on thresholds before beginning the configuration process. the spi flash prom is powered by the same voltage sup- ply feeding the fpga's vcco_2 voltage input, typically 3.3v. spi flash proms specify that they cannot be accessed until their v cc supply reaches its minimum data sheet voltage, followed by an additional delay. for some devices, this additional delay is as little as 10 s as shown in ta b l e 5 6 . for other vendors, this delay is as much as 20 ms. in many systems, the 3.3v supply feeding the fpga's vcco_2 input is valid be fore the fpga's other v ccint and v ccaux supplies, and consequently, there is no issue. how- ever, if the 3.3v supply feeding the fpga's vcco_2 supply is last in the sequence, a potential race occurs between the fpga and the spi flash prom, as shown in figure 55 . done open-drain bidirectional i/o fpga configuration done . low during configuration. goes high when fpga successfully complete s configuration. requires external 330 pull-up resistor to 2.5v. low indicates that the fpga is not yet configured. pulled high via external pull-up. when high, indicates that the fpga successfully configured. prog_b input program fpga . active low. when asserted low for 500 ns or longer, forces the fpga to restart its configuration process by clearing configuration memory and resetting the done and init_b pins once prog_b returns high. recommend external 4.7 k pull-up resistor to 2.5v. internal pull-up value may be weaker (see ta b l e 7 8 ). if driving externally with a 3.3v output, use an open-drain or open-collector driver or use a current limiting series resistor. must be high to allow configuration to start. drive prog_b low and release to reprogram fpga. hold prog_b to force fpga i/o pins into hi-z, allowing direct programming access to spi flash prom pins. ta bl e 5 5 : serial peripheral interface (spi) connections (continued) pin name fpga direction description during configuration after configuration ta bl e 5 6 : example minimum power-on to select times for various spi flash proms vendor spi flash prom part number data sheet minimum time from v cc min to select = low symbol value units stmicroelectronics m25pxx t vsl 10 s spansion s25flxxxa t pu 10 ms nexflash nx25xx t vsl 10 s macronix mx25lxxxx t vsl 10 s silicon storage technology sst25lfxx t pu-read 10 s programmable microelectronics corporation pm25lvxxx t vcs 50 s atmel corporation at45dbxxxd t vcsl 30 s at45dbxxxb 20 ms functional description 82 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r if the fpga's v ccint and v ccaux supplies are already valid, then the fpga waits for vcco_2 to reach its mini- mum threshold voltage before starting configuration. this threshold voltage is labeled as v cco2t in ta bl e 7 4 of mod- ule 3 and ranges from approximately 0.4v to 1.0v, substan- tially lower than the spi flash prom's minimum voltage. once all three fpga supplies reach their respective power on reset (por) thresholds, the fpga starts the configura- tion process and begins initializ ing its internal configuration memory. initialization requir es approximately 1 ms (t por , minimum in table 111 of module 3, after which the fpga de-asserts init_b, selects the spi flash prom, and starts sending the appropriate read command. the spi flash prom must be ready for read operations at this time. spar- tan-3e fpgas issue the read command just once. if the spi flash is not ready, then the fpga does not properly config- ure. if the 3.3v supply is last in the sequence and does not ramp fast enough, or if the spi flash prom cannot be ready when required by the fpga, delay the fpga configuration process by holding either the fpga's prog_b input or init_b input low, as highlighted in figure 54 . release the fpga when the spi flash prom is ready. for example, a simple r-c delay circuit attached to the init_b pin forces the fpga to wait for a preselected amount of time. alter- nately, a power good signal fr om the 3.3v supply or a sys- tem reset signal accomplishes the same purpose. use an open-drain or open-collector output when driving prog_b or init_b. spi flash prom density requirements ta bl e 5 7 shows the smallest usable spi flash prom to program a single spartan-3e fpga. commercially avail- able spi flash proms range in density from 1 mbit to 128 mbits. a multiple-fpga daisy-chained application requires a spi flash prom large enough to contain the sum of the fpga file sizes. an application can also use a larger-den- sity spi flash prom to hold additional data beyond just fpga configuration data. for example, the spi flash prom can also store application code for a microblaze ? risc processor core integrated in the spartan-3e fpga. see using the spi flash interface after configuration . cclk frequency in spi flash mode, the fpga?s internal oscilla tor generates the configuration clock frequency. the fpga provides this clock on its cclk output pin, driving the prom?s clock input pin. the fpga starts configuration at its lowest frequency and increases its frequency for the remainder of the config- uration process if so specified in the configuration bitstream. the maximum frequency is specified using the configrate bitstream generator option. the maximum frequency sup- ported by the fpga configuration logic depends on the tim- ing for the spi flash device. without examining the timing for a specific spi flash prom, use configrate =12 or lower. spi flash proms that support the fast read com- mand support higher data rates. some such proms sup- port up to configrate = 25 and beyond but require careful data sheet analysis. see serial peripheral interface (spi) configuration timing for more detailed timing analysis. using the spi flash interface after configuration after the fpga successfully completes configuration, all of the pins connected to the spi flash prom are available as user-i/o pins. figure 55: spi flash prom/fpga power-on timing if 3.3v supply is last in power-on sequence fpga vcco_2 minim u m power on re s et volt a ge (v cco2t ) s pi fl as h prom minim u m volt a ge s pi fl as h a v a il ab le for re a d oper a tion s s pi fl as h (t v s l ) s pi fl as h c a nnot b e s elected fpga initi a lize s config u r a tion memory 3 . 3 v supply fpga a cce ss e s s pi fl as h prom time s pi fl as h prom m us t b e re a dy for fpga a cce ss , otherwi s e del a y fpga config u r a tion d s3 12-2_50 b _110206 (t por ) (v ccint , v ccaux already valid) prom c s del a y table 57: number of bits to program a spartan-3e fpga and smallest spi flash prom device number of configuration bits smallest usable spi flash prom xc3s100e 581,344 1 mbit xc3s250e 1,353,728 2 mbit xc3s500e 2,270,208 4 mbit xc3s1200e 3,841,184 4 mbit xc3s1600e 5,969,696 8 mbit functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 83 product specification r if not using the spi flash prom after configuration, drive cso_b high to disable the prom. the mosi, din, and cclk pins are then available to the fpga application. because all the interface pins are user i/o after configura- tion, the fpga application can continue to use the spi flash interface pins to communicate with the spi flash prom, as shown in figure 56 . spi flash proms offer ran- dom-accessible, byte-addressable, read/write, non-volatile storage to the fpga application. spi flash proms are available in densities ranging from 1 mbit up to 128 mbits. however, a single spartan-3e fpga requires less than 6 mbits. if desired, use a larger spi flash prom to contain additional non-volatile application data, such as microblaze processor code, or other user data such as serial numbers and ethernet mac ids. in the example shown in figure 56 , the fpga configures from spi flash prom. then using fpga logic after configuration, the fpga copies microblaze code from spi flash into external ddr sdram for code execution. similarly, the fpga appli- cation can store non-volatile application data within the spi flash prom. the fpga configuration data is stored starting at location 0. store any additional data beginning in the next available spi flash prom sector or page. do not mix configuration data and user data in the same sector or page. similarly, the spi bus can be expanded to additional spi peripherals. because spi is a common industry-standard interface, various spi-based peripherals are available, such as analog-to-digital (a/d) converters, digital-to-analog (d/a) converters, can controllers, and temperature sensors. however, if sufficient i/o pins are available in the applica- tion, xilinx recommends creating a separate spi bus to con- trol peripherals. creating a second port reduces the loading on the cclk and din pins, which are crucial for configura- tion. the mosi, din, and cclk pins are common to all spi peripherals. connect the select input on each additional spi peripheral to one of the fpga user i/o pins. if hswap = 0 during configuration, the fpga holds the sele ct line high. if hswap = 1, connect the select line to +3.3v via an external 4.7 k pull-up resistor to avoid spurious read or write oper- ations. after configuration, drive the select line low to select the desired spi peripheral. during the configuration process, cclk is controlled by the fpga and limited to the frequencies generated by the fpga. after configuration, the fpga application can use other clock signals to drive the cclk pin and can further optimize spi-based communication. refer to the individual spi peripheral data sheet for specific interface and communication protocol requirements. figure 56: using the spi flash interface after configuration mo s i din cclk c s o_b data_in data_out clock s elect data_in data_out clock s elect spi serial fla s h prom fpga config u r a tion microbl a ze code u s er d a t a 0 fffff spi peripheral s - a/d converter - d/a converter - can controller - di s pl a y s - temper a t u re s en s or - a ss p u s er i/o 4.7k + 3 . 3 v to other spi slave peripherals spartan- 3 e fpga ddr sdram microblaze d s3 12-2_47_0 8 2009 fpga- bas ed s pi m as ter functional description 84 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r daisy-chaining if the application requires multiple fpgas with different con- figurations, then configure the fpgas using a daisy chain, as shown in figure 57 . daisy-chaining from a single spi serial flash prom is supported in stepping 1 devices. it is not supported in stepping 0 devices. use spi flash mode (m[2:0] = <0:0:1>) for the fpga connected to the platform flash prom and slave serial mode (m[2:0] = <1:1:1>) for all other fpgas in the daisy-chain. after the master fpga?the fpga on the left in the diagram?finishes load- ing its configuration data from the spi flash prom, the master device uses its dout output pin to supply data to the next device in the daisy-chain, on the falling cclk edge. design note spi mode daisy chains are supported only in stepping 1 sil- icon versions. programming support for successful daisy-chaining, the done_cycle configura- tion option must be set to cycle 5 or sooner. the default cycle is 4. see ta b l e 6 9 and the start-up section for addi- tional information. in production applications, the spi flash prom is usu- ally pre-programmed before it is mounted on the printed cir- cuit board. the xilinx ise development software produces industry-standard programming files that can be used with third-party gang programmers. consult your specific spi flash vendor for recommended production programming solutions. in-system programming support is available from some third-party prom programmers using a socket adapter with attached wires. to gain access to the spi flash signals, drive the fpga?s prog_b input low with an open-drain driver. this action places all fpga i/o pins, including those attached to the spi flash, in high-impedance (hi-z). if the hswap input is low, the i/os have pull-up resistors to the v cco input on their respective i/o bank. the external pro- gramming hardware then has di rect access to the spi flash pins. the programming access points are highlighted in the gray box in figure 53 , figure 54 , and figure 57 . beginning with the xilinx ise 8. 2i software release, the impact programming utility provides direct, in-system pro- totype programming support for stmicro m25p-series spi serial flash proms and the atmel at45db-series data flash proms using the platform cable usb , x ilinx parallel iv , or other compatible programming cable. figure 57: daisy-chaining from spi flash mode (stepping 1) +2.5v tdi tdo tm s tck vccint vccaux +2.5v c s o_b vcco_2 init_b din mo s i prog_b done gnd +1.2v data _ i n s elect vcc data _ o u t clock gnd h s wap vcco_0 p cclk tdi tdo tm s tck vccint vccaux din dout vcco_2 init_b prog_b done gnd +1.2v m2 m1 ?1? ?1? m0 h s wap vcco_0 p + 3 . 3 v +2.5v ?1? vcco_0 4.7k slave serial mode +2.5v jtag cclk init_b done prog_b tck tm s spi serial fla s h prog_b recommend open-drain driver vcco_0 tdi tm s tck tdo + 3 . 3 v + 3 . 3 v hold ?1? m2 m1 ?0? ?0? m0 spi mode ?1? v s 2 v s 1 ?1? v s 0 variant select ?1? s dout spartan- 3 e fpga spartan- 3 e fpga dout cclk wr_protect w + 3 . 3 v p 4.7k 33 0 i 4.7k d s3 12-2_4 8 _0 8 2009 ! spi-ba s ed dai s y-chaining i s only s upported in stepping 1. i functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 85 product specification r byte-wide peripheral in terface (bpi) parallel flash mode for additional informat ion, refer to the ? master bpi mode ? chapter in ug332 . in byte-wide peripheral interface (bpi) mode (m[2:0] = <0:1:0> or <0:1:1>), a spartan-3e fpga config- ures itself from an industry-standard parallel nor flash prom, as illustrated in figure 58 . the fpga generates up to a 24-bit address lines to access an attached parallel flash. only 20 address lines are generated for spartan-3e fpgas in the tq144 package. similarly, the xc3s100e fpga in the cp132 package only has 20 address lines while the xc3s250e and xc3s500e fpgas in the same package have 24 address lines. when using the vq100 package, the bpi mode is not available when using parallel nor flash, but is supported using parallel platform flash (xcfxxp). the bpi configuration interface is primarily designed for standard parallel nor flash proms and supports both byte-wide (x8) and byte-wide/halfword (x8/x16) proms. the interface functions with halfword-only (x16) proms, but the upper byte in a portion of the prom remains unused. for configuration, the bpi interface does not require any specific flash prom features, such as boot block or a specific sector size. the bpi interface also functi ons with xilinx parallel platform flash proms (xcfxxp), although the fpga?s address lines are left unconnected. the bpi interface also works equally wells with other asyn- chronous memories that use a similar sram-style interface such as sram, nvram, eeprom, eprom, or masked rom. nand flash memory is commonly used in memory cards for digital cameras. spartan-3e fpgas do not configure directly from nand flash memories. the fpga?s internal oscillator controls the interface timing and the fpga supplies the clock on the cclk output pin. however, the cclk signal is not used in single fpga appli- cations. similarly, the fpga drives three pins low during configuration (ldc[2:0]) and one pin high during configura- tion (hdc) to the prom?s control inputs. functional description 86 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r during configuration, the value of the m0 mode pin determines how the fpga generates addresses, as shown ta bl e 5 8 . when m0 = 0, the fpga generates addresses starting at 0 and increments the address on every falling cclk edge. conversely, when m0 = 1, the fpga gener- ates addresses starting at 0xff_ffff (all ones) and decre- ments the address on every falling cclk edge. figure 58: byte-wide peripheral interface (bpi) mode co nfigured from parallel nor flash proms tdi tdo tm s tck vccint vccaux +2.5v hdc cclk c s o_b vcco_1 init_b c s i_b d[7:0] ldc1 ldc0 ?0? a[16:0] prog_b done gnd vcco_2 +1.2v dq[7:0] a[n:0] ce# we# vcco oe# byte# dq[15:7] gnd m2 m1 ?0? ?1? m0 h s wap vcco_0 a a[2 3 :17] p ldc2 vcco_0 v v v bpi mode +2.5v jtag x 8 or x 8 /x16 fla s h prom prog_b recommend open-drain driver tdi tm s tck tdo rdwr_b ?0? spartan- 3 e fpga bu s y i not available in vq100 package v 4.7k +2.5v 4.7k 3 3 0 d s3 12-2_49_0 8 2009 d a table 58: bpi addressing control m2 m1 m0 start address addressing 0 1 0 0 incrementing 1 0xff_ffff decrementing functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 87 product specification r this addressing flexibility allows the fpga to share the par- allel flash prom with an external or embedded processor. depending on the specific processor architecture, the pro- cessor boots either from the top or bottom of memory. the fpga is flexible and boots from the opposite end of mem- ory from the processor. only the processor or the fpga can boot at any given time. the fpga can configure first, hold- ing the processor in reset or the processor can boot first, asserting the fpga?s prog_b pin. the mode select pins, m[2:0], are sampled when the fpga?s init_b output goes high and must be at defined logic levels during this time. after configuration, when the fpga?s done output goes high, the mode pins are avail- able as full-featured user-i/o pins. similarly, the fpga?s hswap pin must be low to enable pull-up resistors on all user-i/o pins or high to dis- able the pull-up resistors. the hswap control must remain at a constant logic level throughout fpga configuration. after configuration, when the fpga?s done output goes high, the hswap pin is available as full-featured user-i/o pin and is powered by the vcco_0 supply. the rdwr_b and csi_b must be low throughout the con- figuration process. after configuration, these pins also become user i/o. in a single-fpga application, the fpga?s cso_b and cclk pins are not used but are actively driving during the configuration process. the busy pin is not used but also actively drives during configuration and is available as a user i/o after configuration. after configuration, all of the interface pins except done and prog_b are available as user i/os. furthermore, the bidirectional selectmap configuration peripheral interface (see slave parallel mode ) is available after configuration. to continue using selectmap mode, set the persist bit- stream generator option to yes . an external host can then read and verify configuration data. the persist option will maintain a20-a23 as configuration pins although they are not used in selectmap mode. p ta bl e 5 9 : byte-wide peripheral interface (bpi) connections pin name fpga direction description during configuration after configuration hswap input user i/o pull-up control . when low during configuration, enables pull-up resistors in all i/o pins to respective i/o bank v cco input. 0: pull-ups during configuration 1: no pull-ups drive at valid logic level throughout configuration. user i/o m[2:0] input mode select . selects the fpga configuration mode. see design considerations for the hswap, m[2:0], and vs[2:0] pins . m2=0, m1=1. set m0=0 to start at address 0, increment addresses. set m0 = 1 to start at address 0xffffff and decrement addresses. sampled when init_b goes high. user i/o csi_b input chip select input . active low. must be low throughout configuration. user i/o. if bitstream option persist=yes , becomes part of selectmap parallel peripheral interface. rdwr_b input read/write control . active low write enable. read functionality typically only used after configuration, if bitstream option persist=yes . must be low throughout configuration. user i/o. if bitstream option persist=yes , becomes part of selectmap parallel peripheral interface. ldc0 output prom chip enable connect to prom chip-select input (ce#). fpga drives this signal low throughout configuration. user i/o. if the fpga does not access the prom after configuration, drive this pin high to deselect the prom. a[23:0], d[7:0], ldc[2:1], and hdc then become available as user i/o. p a functional description 88 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r ldc1 output prom output enable connect to the prom output-enable input (oe#). the fpga drives this signal low throughout configuration. user i/o hdc output prom write enable connect to prom write-enable input (we#). fpga drives this signal high throughout configuration. user i/o ldc2 output prom byte mode this signal is not used for x8 proms. for proms with a x8/x16 data width control, connect to prom byte-mode input (byte#). see precautions using x8/x16 flash proms . fpga drives this signal low throughout configuration. user i/o. drive this pin high after configuration to use a x8/x16 prom in x16 mode. a[23:0] output address connect to prom address inputs. high-order address lines may not be available in all packages and not all may be required. number of address lines required depends on the size of the attached flash prom. fpga address generation controlled by m0 mode pin. addresses presented on falling cclk edge. only 20 address lines are available in tq144 package. user i/o d[7:0] input data input fpga receives byte-wide data on these pins in response the address presented on a[23:0]. data captured by fpga on rising edge of cclk. user i/o. if bitstream option persist=yes , becomes part of selectmap parallel peripheral interface. cso_b output chip select output . active low. not used in single fpga applications. in a daisy-chain configuration, this pin connects to the csi_b pin of the next fpga in the chain. if hswap = 1 in a multi-fpga daisy-chain application, connect this signal to a 4.7 k pull-up resistor to vcco_2. actively drives low when selecting a downstream device in the chain. user i/o busy output busy indicator . typically only used after configuration, if bitstream option persist=yes . not used during configuration but actively drives. user i/o. if bitstream option persist=yes , becomes part of selectmap parallel peripheral interface. ta bl e 5 9 : byte-wide peripheral interface (bpi) connections (continued) pin name fpga direction description during configuration after configuration d functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 89 product specification r voltage compatibility the fpga?s parallel flash interface signals are within i/o banks 1 and 2. the majority of parallel flash proms use a single 3.3v supply voltage. consequently, in most cases, the fpga?s vcco_1 and vcco_2 supply voltages must also be 3.3v to match the parallel flash prom. there are some 1.8v parallel flash proms available and the fpga interfaces with these devices if the vcco_1 and vcco_2 supplies are also 1.8v. power-on precautions if prom supply is last in sequence like spi flash proms, parallel flash proms typically require some amount of internal initialization time when the supply voltage reaches its minimum value. the prom supply voltage also connects to the fpga?s vcco_2 supply input. in many systems, the prom supply feeding the fpga?s vcco_2 input is valid before the fpga?s other v ccint and v ccaux supplies, and conse- quently, there is no issue. however, if the prom supply is last in the sequence, a potential race occurs between the fpga and the parallel flash prom. see power-on pre- cautions if 3.3v supply is last in sequence for a similar description of the issue for spi flash proms. supported parallel nor flash prom densities ta b l e 6 0 indicates the smallest usable parallel flash prom to program a single spartan-3e fpga. parallel flash den- sity is specified in bits but addressed as bytes. the fpga presents up to 24 address lines during configuration but not all are required for single fpga applications. ta bl e 6 0 cclk output configuration clock . generated by fpga internal oscillator. frequency controlled by configrate bitstream generator option. if cclk pcb trace is long or has multiple connections, terminate this output to maintain signal integrity. see cclk design considerations . not used in single fpga applications but actively drives. in a daisy-chain configuration, drives the cclk inputs of all other fpgas in the daisy-chain. user i/o. if bitstream option persist=yes , becomes part of selectmap parallel peripheral interface. init_b open-drain bidirectional i/o initialization indicator . active low. goes low at start of configuration during the initialization memory clearing process. released at the end of memory clearing, when the mode select pins are sampled. in daisy-chain applications, this signal requires an external 4.7 k pull-up resistor to vcco_2. active during configuration. if crc error detected during configuration, fpga drives init_b low. user i/o. if unused in the application, drive init_b high. done open-drain bidirectional i/o fpga configuration done . low during configuration. goes high when fpga successfully completes configuration. requires external 330 pull-up resistor to 2.5v. low indicates that the fpga is not yet configured. pulled high via external pull-up. when high, indicates that the fpga is successfully configured. prog_b input program fpga . active low. when asserted low for 500 ns or longer, forces the fpga to restart its configuration process by clearing configuration memory and resetting the done and init_b pins once prog_b returns high. recommend external 4.7 k pull-up resistor to 2.5v. internal pull-up value may be weaker (see ta b l e 7 8 ). if driving externally with a 3.3v output, use an open-drain or open-collector driver or use a current limiting series resistor. must be high to allow configuration to start. drive prog_b low and release to reprogram fpga. hold prog_b to force fpga i/o pins into hi-z, allowing direct programming access to flash prom pins. ta bl e 5 9 : byte-wide peripheral interface (bpi) connections (continued) pin name fpga direction description during configuration after configuration v functional description 90 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r shows the minimum required number of address lines between the fpga and parallel flash prom. the actual number of address line required depends on the density of the attached parallel flash prom. a multiple-fpga daisy-chained application requires a paral- lel flash prom large enough to contain the sum of the fpga file sizes. an application can also use a larger-density parallel flash prom to hold additional data beyond just fpga configuration data. for example, the parallel flash prom can also contain the application code for a microblaze risc processor core implemented within the spartan-3e fpga. after configuration, the microblaze processor can execute directly from external flash or can copy the code to other, faster system memory before executing the code. compatible flash families the spartan-3e bpi configuration interface operates with a wide variety of x8 or x8/x16 parallel nor flash devices. ta bl e 6 1 provides a few flash memo ry families that operate with the spartan-3e bpi interface. consult the data sheet for the desired parallel nor flas h to determine its suitability the basic timing requirements and waveforms are provided in byte peripheral interface (bpi) configuration timing (module 3). cclk frequency in bpi mode, the fpga?s inte rnal oscillator generates the configuration clock frequency that controls all the interface timing. the fpga starts configuration at its lowest fre- quency and increases its frequency for the remainder of the configuration process if so specified in the configuration bit- stream. the maximum frequency is specified using the configrate bitstream generator option. ta b l e 6 2 shows the maximum configrate settings for vari- ous typical prom read access times over the commercial temperature operating range. see byte peripheral inter- face (bpi) configuration timing (module 3) and ug332 for more detailed information. despite using slower configrate settings, bpi mode is equally fast as the other configuration modes. in bpi mode, data is accessed at the configrate frequency and internally serialized with an 8x clock frequency. using the bpi interface after configuration after the fpga successfully completes configuration, all pins connected to the parallel flash prom are available as user i/os. if not using the parallel flash prom after configuration, drive ldc0 high to disable the prom?s chip-select input. the remainder of the bpi pins then become available to the fpga application, including all 24 address lines, the eight data lines, and the ldc2, ldc1, and hdc control pins. because all the interface pins are user i/os after configura- tion, the fpga application can continue to use the interface pins to communicate with the parallel flash prom. parallel flash proms are available in densities ranging from 1 mbit up to 128 mbits and beyond. however, a single spartan-3e fpga requires less than 6 mbits for configuration. if ta bl e 6 0 : number of bits to program a spartan-3e fpga and smallest parallel flash prom spartan-3e fpga uncompressed file sizes (bits) smallest usable parallel flash prom minimum required address lines xc3s100e 581,344 1 mbit a[16:0] xc3s250e 1,353,728 2 mbit a[17:0] xc3s500e 2,270,208 4 mbit a[18:0] xc3s1200e 3,841,184 4 mbit a[18:0] xc3s1600e 5,969,696 8 mbit a[19:0] ta bl e 6 1 : compatible parallel nor flash families flash vendor flash memory family numonyx m29w, j3d strataflash atmel at 2 9 / at 4 9 spansion s29 macronix mx29 table 62: maximum configrate settings for parallel flash proms (commercial temperature range) flash read access time maximum configrate setting 250 ns 3 115 ns 6 45 ns 12 functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 91 product specification r desired, use a larger parallel flash prom to contain addi- tional non-volatile application data, such as microblaze pro- cessor code, or other user data, such as serial numbers and ethernet mac ids. in such an example, the fpga config- ures from parallel flash prom. then using fpga logic after configuration, a microblaze processor embedded within the fpga can either execute code directly from par- allel flash prom or copy the code to external ddr sdram and execute from ddr sdram. similarly, the fpga application can store non-volatile application data within the parallel flash prom. the fpga configuration data is stored starting at either at location 0 or the top of memory (addresses all ones) or at both locations for multiboot mode. store any additional data beginning in other available parallel flash prom sectors. do not mix configuration data and user data in the same sector. similarly, the parallel flash prom interface can be expanded to additional parallel peripherals. the address, data, and ldc1 (oe#) and hdc (we#) con- trol signals are common to all parallel peripherals. connect the chip-select input on each additional peripheral to one of the fpga user i/o pins. if hswap = 0 during configuration, the fpga holds the chip-select line high via an internal pull-up resistor. if hswap = 1, connect the select line to +3.3v via an external 4.7 k pull-up resistor to avoid spuri- ous read or write operations. after configuration, drive the select line low to select the de sired peripheral. refer to the individual peripheral data sheet for specific interface and communication protocol requirements. the fpga optionally supports a 16-bit peripheral interface by driving the ldc2 (byte#) control pin high after configu- ration. see precautions using x8/x16 flash proms for additional information. the fpga provides up to 24 address lines during configu- ration, addressing up to 128 mbits (16 mbytes). if using a larger parallel prom, connect the upper address lines to fpga user i/o. during configuration, the upper address lines will be pulled high if hswap = 0. otherwise, use external pull-up or pull-down resistors on these address lines to define their values during configuration. precautions using x8/x16 flash proms most low- to mid-density proms are byte-wide (x8) only. many higher-density flash proms support both byte-wide (x8) and halfword-wide (x16) data paths and include a mode input called byte# that switches between x8 or x16. during configuration, spartan-3e fpgas only support byte-wide data. however, after configuration, the fpga supports either x8 or x16 modes. in x16 mode, up to eight additional user i/o pins are required for the upper data bits, d[15:8]. connecting a spartan-3e fpga to a x8/x16 flash prom is simple, but does require a precaution. various flash prom vendors use slightly different interfaces to support both x8 and x16 modes. some vendors (intel, micron, some stmi- croelectronics devices) use a straightforward interface with pin naming that matches the fpga connections. however, the prom?s a0 pin is wasted in x16 applications and a sep- arate fpga user-i/o pin is required for the d15 data line. fortunately, the fpga a0 pin is still available as a user i/o after configuration, even though it connects to the flash prom. other vendors (amd, atmel, silicon storage technology, some stmicroelectronics device s) use a pin-efficient inter- face but change the function of one pin, called io15/a-1, depending if the prom is in x8 or x16 mode. in x8 mode, byte# = 0, this pin is the least-significant address line. the a0 address line selects the halfword location. the a-1 address line selects the byte location. when in x16 mode, byte# = 1, the io15/a-1 pin becomes the most-significant data bit, d15 because byte addressing is not required in this mode. check to see if the flash prom has a pin named ?io15/a-1? or ?dq15/a-1?. if so, be careful to connect x8/x16 flash proms correctly, as shown in ta b l e 6 3 . also, remember that the d[14:8] data connections require fpga user i/o pins but that the d15 data is already connected for the fpga?s a0 pin. d ta bl e 6 3 : fpga connections to flash prom with io15/a-1 pin fpga pin connection to flash prom with io15/a-1 pin x8 flash prom interface after fpga configuration x16 flash prom interface after fpga configuration ldc2 byte# drive ldc2 low or leave unconnected and tie prom byte# input to gnd drive lcd2 high ldc1 oe# active-low flash prom output-enable control active-low flash prom output-enable control ldc0 cs# active-low flash prom chip-select control active-low flash prom chip-select control hdc we# flash prom write-enable control flash prom write-enable control functional description 92 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r some x8/x16 flash proms have a long setup time require- ment on the byte# signal. for the fpga to configure cor- rectly, the prom must be in x8 mode with byte# = 0 at power-on or when the fpga?s prog_b pin is pulsed low. if required, extend the byte# setup time for a 3.3v prom using an external 680 pull-down resistor on the fpga?s ldc2 pin or by delaying assertion of the csi_b select input to the fpga. daisy-chaining if the application requires multiple fpgas with different con- figurations, then configure the fpgas using a daisy chain, as shown in figure 59 . use bpi mode (m[2:0] = <0:1:0> or <0:1:1>) for the fpga connected to the parallel nor flash prom and slave parallel mode (m[2:0] = <1:1:0>) for all downstream fpgas in the daisy-chain. if there are more than two fpgas in the chain, then last fpga in the chain can be from any xilinx fpga family. however, all intermedi- ate fpgas located in the chain between the first and last fpgas must from either the spartan-3e or virtex?-5 fpga families. after the master fpga?the fpga on the left in the dia- gram?finishes loading its configuration data from the paral- lel flash prom, the master device continues generating addresses to the flash prom and asserts its cso_b out- put low, enabling the next fpga in the daisy-chain. the next fpga then receives parallel configuration data from the flash prom. the master fpga?s cclk output syn- chronizes data capture. if hswap = 1, an external 4.7k pull-up resistor must be added on the cso_b pin. if hswap = 0, no external pull-up is necessary. design note bpi mode daisy chain software support is available starting in ise 8.2i. http://www.xilinx.com/supp ort/answers/23061.htm also, in a multi-fpga daisy-chain configuration of more than two devices, all intermediate fpgas between the first and last devices must be spartan-3e or virtex-5 fpgas. the last fpga in the chain can be from any xilinx fpga family. bpi mode interaction with right and bottom edge global clock inputs some of the bpi mode configuration pins are shared with global clock inputs along the right and bottom edges of the device (bank 1 and bank 2, re spectively). these pins are not easily reclaimable for clock inputs after configuration, especially if the fpga applic ation access the parallel nor flash after configuration. ta b l e 6 4 summarizes the shared pins. a[23:1] a[n:0] a[n:0] a[n:0] a0 io15/a-1 io15/a-1 is the least-significant address input io15/a-1 is the most-significant data line, io15 d[7:0] io[7:0] io[7:0] io[7:0] user i/o upper data lines io[14:8] not required unless used as x16 flash interface after configuration upper data lines io[14:8] not required io[14:8] ta bl e 6 3 : fpga connections to flash prom with io15/a-1 pin (continued) fpga pin connection to flash prom with io15/a-1 pin x8 flash prom interface after fpga configuration x16 flash prom interface after fpga configuration table 64: shared bpi configuration mode and global buffer input pins device edge global buffer input pin bpi mode configuration pin bottom gclk0 rdwr_b gclk2 d2 gclk3 d1 gclk12 d7 gclk13 d6 gclk14 d4 gclk15 d3 right rhclk0 a10 rhclk1 a9 rhclk2 a8 rhclk3 a7 rhclk4 a6 rhclk5 a5 rhclk6 a4 rhclk7 a3 functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 93 product specification r stepping 0 limitations when reprogramming via jtag if fpga set for bpi configuration the fpga can always be reprogrammed via the jtag port, regardless of the mode pin (m[2:0]) settings. however, stepping 0 devices have a minor limitation. if a stepping 0 fpga is set to configure in bpi mode and the fpga is attached to a parallel memory containing a valid fpga con- figuration file, then subsequent reconfigurations using the jtag port will fail. potential wo rkarounds include setting the mode pins for jtag configuration (m[2:0] = <1:0:1>) or off- setting the initial memory location in flash by 0x2000. stepping 1 devices fully support jtag configuration even when the fpga mode pins are set for bpi mode. in-system programming support in a production application, the parallel flash prom is usually preprogrammed before it is mounted on the printed circuit board. in-system programming support is available from third-party boundary-scan tool vendors and from some third-party prom programmers using a socket adapter with attached wires. to gain access to the parallel flash signals, drive the fpga?s prog_b input low with an open-drain driver. this action places all fpga i/o pins, including those attached to the parallel flash, in high-impedance (hi-z). if the hswap input is low, the i/os have pull-up resistors to the v cco input on their respective i/o bank. the external programming hardware then has direct access to the paral- lel flash pins. the programming access points are high- lighted in the gray boxes in figure 58 and figure 59 . the fpga itself can also be used as a parallel flash prom programmer during development and test phases. initially, an fpga-based programmer is downloaded into the fpga via jtag. then the fpga performs the flash prom pro- gramming algorithms and receives programming data from the host via the fpga?s jtag interface. see the embedded system tools reference manual. dynamically loading multiple configuration images using multiboot option for additional information, refer to the ? reconfiguration and multiboot ? chapter in ug332 . figure 59: daisy-chaining from bpi flash mode +2.5v tdi tdo tm s tck vccint vccaux +2.5v hdc cclk c s o_b vcco_1 init_b c s i_b d[7:0] ldc1 ldc0 ?0? a[16:0] prog_b done gnd vcco_2 +1.2v dq[7:0] a[n:0] ce# we# vcc oe# byte# dq[15:7] gnd m2 m1 ?0? ?1? m0 h s wap vcco_0 a a[2 3 :17] p ldc2 tdi tdo tm s tck vccint vccaux cclk c s o_b vcco_1 init_b c s i_b d[7:0] prog_b done gnd vcco_2 +1.2v m2 m1 ?1? ?1? m0 h s wap vcco_0 p vcco_1 +2.5v ?0? vcco_0 v v v v d v bpi mode slave parallel mode 2.5v jtag cclk d[7:0] init_b done prog_b tck tm s x 8 or x 8 /x16 fla s h prom prog_b recommend open-drain driver vcco_0 tdi tm s tck tdo rdwr_b ?0? c s o_b rdwr_b ?0? bu s y spartan- 3 e fpga spartan- 3 e fpga bu s y i 33 0 4.7k 4.7k not available in vq100 package d s3 12-2_50_0 8 2009 4.7k i functional description 94 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r after the fpga configures itself using bpi mode from one end of the parallel flash prom, then the fpga can trigger a multiboot event and reconfigure itself from the opposite end of the parallel flash prom. multiboot is only available when using bpi mode and only for applications with a single spartan-3e fpga. by default, multiboot mode is disabled. to trigger a multi- boot event, assert a low pulse lasting at least 300 ns on the multiboot trigger (mbt) input to the startup_spartan3e library primitive . when the mbt signal returns high after the 300 ns or longer pulse, the fpga automatically reconfig- ures from the opposite end of the parallel flash memory. figure 60 shows an example usage. at power up, the fpga loads itself from the attached parallel flash prom. in this example, the m0 mode pin is low so the fpga starts at address 0 and increments through the flash prom mem- ory locations. after the fpga completes configuration, the application initially loaded into the fpga performs a board-level or system test using fpga logic. if the test is successful, the fpga then trig gers a multiboot event, caus- ing the fpga to reconfigure from the opposite end of the flash prom memory. this second configuration contains the fpga application for normal operation. similarly, the general fpga application could trigger another multiboot event at any time to reload the diagnos- tics design, and so on. in another potential ap plication, the initia l design loaded into the fpga image contains a ?golden? or ?fail-safe? configura- tion image, which then communicates with the outside world and checks for a newer image. if there is a new configura- tion revision and the new image verifies as good, the ?golden? configuration triggers a multiboot event to load the new image. when a multiboot event is triggered, the fpga then again drives its configuration pins as described in ta bl e 5 9 . how- ever, the fpga does not assert the prog_b pin. the sys- tem design must ensure that no other device drives on these same pins during the reconfiguration process. the fpga?s done, ldc[2:0], or hdc pins can temporarily dis- able any conflicting drivers during reconfiguration. asserting the prog_b pin low overrides the multiboot fea- ture and forces the fpga to reconfigure starting from the end of memory defined by the mode pins, shown in ta b l e 5 8 . figure 60: use multiboot to load alternate configuration images gsr gts mbt clk startup_spartan3e 0 ffffff general fpga application di a g nostics fpga application parallel flash prom > 300 ns user area 0 ffffff general fpga application di a g nostics fpga application p arallel flash prom user area first confi g uration second confi g uration reconfigure DS312-2_51_103105 functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 95 product specification r slave parallel mode for additional informat ion, refer to the ? slave parallel (selectmap) mode ? chapter in ug332 . in slave parallel mode (m[2:0] = <1:1:0>), an external host, such as a microprocessor or microcontroller, writes byte-wide configuration data into the fpga, using a typical peripheral interface as shown in figure 61 . the external download host starts the configuration process by pulsing prog_b and monitoring that the init_b pin goes high, indicating that the fpga is ready to receive its first data. the host asserts the active-low chip-select signal (csi_b) and the active-low write signal (rdwr_b). the host then continues supplying data and clock signals until either the fpga?s done pin goes high, indicating a suc- cessful configuration, or until the fpga?s init_b pin goes low, indicating a configuration error. the fpga captures data on the rising cclk edge. if the cclk frequency exceeds 50 mhz, then the host must also monitor the fpga?s busy output. if the fpga asserts busy high, the host must hold the data for an additional clock cycle, until busy returns low. if the cclk frequency is 50 mhz or below, the busy pin may be ignored but actively drives during configuration. the configuration process requires more clock cycles than indicated from the configuration file size. additional clocks are required during the fpga?s start-up sequence, espe- cially if the fpga is programmed to wait for selected digital clock managers (dcms) to lock to their respective clock inputs (see start-up , page 107 ). if the slave parallel interface is only used to configure the fpga, never to read data back, then the rdwr_b signal figure 61: slave parallel configuration mode +2.5v prog_b recommend open-drain driver +2.5v jtag tdi tm s tck tdo d[7:0] bu s y s elect read/write clock prog_b init_b done tdi tdo tm s tck vccint vccaux c s o_b init_b c s i_b prog_b done gnd vcco_2 +1.2v m2 m1 ?1? ?1? m0 h s wap vcco_0 p cclk d[7:0] ?0? vcco_0 v rdwr_b spartan- 3 e fpga bu s y slave parallel mode v v 4.7 +2.5v 33 0 4.7k vcc gnd config u r a tion memory s o u rce - intern a l memory - di s k drive - over network - over rf link intelligent download ho s t - microcontroller - proce ss or - te s ter - comp u ter d s3 12-2_52_0 8 2009 functional description 96 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r can also be eliminated from the interface. however, rdwr_b must remain lo w during configuration. after configuration, all of the interface pins except done and prog_b are available as user i/os. alternatively, the bidirectional selectmap configur ation interface is available after configuration. to continue using selectmap mode, set the persist bitstream generator option to yes . the external host can then read and verify configuration data. the persist option will maintain a20-a23 as configuration pins although they are not used in selectmap mode. the slave parallel mode is also used with bpi mode to cre- ate multi-fpga daisy-chains. the lead fpga is set for bpi mode configuration; all the downstream daisy-chain fpgas are set for slave parallel configuration, as highlighted in figure 59 . ta bl e 6 5 : slave parallel mode connections pin name fpga direction description during configuration after configuration hswap input user i/o pull-up control . when low during configuration, enables pull-up resistors in all i/o pins to respective i/o bank v cco input. 0: pull-ups during configuration 1: no pull-ups drive at valid logic level throughout configuration. user i/o m[2:0] input mode select . selects the fpga configuration mode. see design considerations for the hswap, m[2:0], and vs[2:0] pins . m2=1, m1=1, m0=0 sampled when init_b goes high. user i/o d[7:0] input data input . byte-wide data provided by host. fpga captures data on rising cclk edge. user i/o. if bitstream option persist=yes , becomes part of selectmap parallel peripheral interface. busy output busy indicator . if cclk frequency is < 50 mhz, this pin may be ignored. when high, indicates that the fpga is not ready to receive additional configuration data. host must hold data an additional clock cycle. user i/o. if bitstream option persist=yes , becomes part of selectmap parallel peripheral interface. csi_b input chip select input . active low. must be low throughout configuration. user i/o. if bitstream option persist=yes , becomes part of selectmap parallel peripheral interface. rdwr_b input read/write control . active low write enable. must be low throughout configuration. user i/o. if bitstream option persist=yes , becomes part of selectmap parallel peripheral interface. cclk input configuration clock . if cclk pcb trace is long or has multiple connections, terminate this output to maintain signal integrity. see cclk design considerations . external clock. user i/o if bitstream option persist=yes , becomes part of selectmap parallel peripheral interface. cso_b output chip select output . active low. not used in single fpga applications. in a daisy-chain configuration, this pin connects to the csi_b pin of the next fpga in the chain. actively drives. user i/o functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 97 product specification r voltage compatibility most slave parallel interface signals are within the fpga?s i/o bank 2, supplied by the vcco_2 supply input. the vcco_2 voltage can be 1.8v, 2.5v, or 3.3v to match the requirements of the external host, ideally 2.5v. using 1.8v or 3.3v requires additional design considerations as the done and prog_b pins are powered by the fpga?s 2.5v v ccaux supply. see x app453 : the 3.3v configura- tion of spartan-3 fpgas for additional information. daisy-chaining if the application requires mu ltiple fpgas with different con- figurations, then configure the fpgas using a daisy chain. use slave parallel mode (m[2:0 ] = <1:1:0>) for all fpgas in the daisy-chain. the schematic in figure 62 is optimized for fpga downloading and does not support the selectmap read interface. the fpga?s rdwr_b pin must be low dur- ing configuration. after the lead fpga is filled with its configuration data, the lead fpga enables the next fpga in the daisy-chain by asserting is chip-select output, cso_b. init_b open-drain bidirectional i/o initialization indicator . active low. goes low at the start of configuration during the initialization memory clearing process. released at the end of memory clearing, when mode select pins are sampled. in daisy-chain applications, this signal requires an external 4.7 k pull-up resistor to vcco_2. active during configuration. if crc error detected during configuration, fpga drives init_b low. user i/o. if unused in the application, drive init_b high. done open-drain bidirectional i/o fpga configuration done . low during configuration. goes high when fpga successfully completes configuration. requires external 330 pull-up resistor to 2.5v. low indicates that the fpga is not yet configured. pulled high via external pull-up. when high, indicates that the fpga successfully configured. prog_b input program fpga . active low. when asserted low for 500 ns or longer, forces the fpga to restart its configuration process by clearing configuration memory and resetting the done and init_b pins once prog_b returns high. recommend external 4.7 k pull-up resistor to 2.5v. internal pull-up value may be weaker (see ta b l e 7 8 ). if driving externally with a 3.3v output, use an open-drain or open-collector driver or use a current limiting series resistor. must be high to allow configuration to start. drive prog_b low and release to reprogram fpga. ta bl e 6 5 : slave parallel mode connections (continued) pin name fpga direction description during configuration after configuration v functional description 98 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r slave serial mode for additional information, refer to the ? slave serial mode ? chapter in ug332 . in slave serial mode (m[2:0] = <1:1:1>), an external host such as a microprocessor or microcontroller writes serial configuration data into the fpga, using the synchronous serial interface shown in figure 63 . the serial configuration data is presented on the fpga?s din input pin with suffi- cient setup time before each rising edge of the externally generated cclk clock input. the intelligent host starts the configuration process by puls- ing prog_b and monitoring that the init_b pin goes high, indicating that the fpga is ready to receive its first data. the host then continues supplying data and clock signals until either the done pin goes high, indicating a successful configuration, or until the init_b pin goes low, indicating a configuration error. the configuration process requires more clock cycles than indicated from the configuration file size. additional clocks are required during the fpga?s start-up sequence, especially if the fpga is programmed to wait for selected digital clock managers (dcms) to lock to their respective clock inputs (see start-up , page 107 ). figure 62: daisy-chaining using slave parallel mode +2.5v prog_b recommend open-drain driver 2.5v jtag tdi tm s tck tdo data[7:0] bu s y s elect read/write clock prog_b init_b done init_b done prog_b tck tm s c s o_b tdi tdo tm s tck vccint vccaux hdc c s o_b vcco_1 init_b c s i_b ldc1 ldc0 prog_b done gnd vcco_2 +1.2v m2 m1 ?1? ?1? m0 h s wap vcco_0 p ldc2 cclk d[7:0] ?0? vcco_0 v rdwr_b bu s y slave parallel mode vcco_1 tdi tdo tm s tck vccint vccaux hdc c s o_b vcco_1 init_b c s i_b ldc1 ldc0 prog_b done gnd vcco_2 +1.2v m2 m1 ?1? ?1? m0 h s wap vcco_0 p ldc2 cclk d[7:0] ?0? vcco_0 v rdwr_b spartan- 3 e fpga spartan- 3 e fpga bu s y slave parallel mode vcco_1 +2.5v v d[7:0] cclk +2.5v 33 0 4.7k vcc gnd config u r a tion memory s o u rce ? intern a l memory ? di s k drive ? over network ? over rf link intelligent download ho s t ? microcontroller ? proce ss or ? te s ter ?0? ?0? v 4.7k d s3 12-2_5 3 _0 8 2009 functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 99 product specification r the mode select pins, m[2:0], are sampled when the fpga?s init_b output goes high and must be at defined logic levels during this time. after configuration, when the fpga?s done output goes high, the mode pins are avail- able as full-featured user-i/o pins. similarly, the fpga?s hswap pin must be low to enable pull-up resistors on all user-i/o pins or high to dis- able the pull-up resistors. the hswap control must remain at a constant logic level throughout fpga configuration. after configuration, when the fpga?s done output goes high, the hswap pin is available as full-featured user-i/o pin and is powered by the vcco_0 supply. voltage compatibility most slave serial interface signals are within the fpga?s i/o bank 2, supplied by the vcco_2 supply input. the vcco_2 voltage can be 3.3v, 2.5v, or 1.8v to match the requirements of the external host, ideally 2.5v. using 3.3v or 1.8v requires additional design considerations as the done and prog_b pins are powered by the fpga?s 2.5v v ccaux supply. see xapp453 : the 3.3v configura- tion of spartan-3 fpgas for additional information. daisy-chaining if the application requires mu ltiple fpgas with different con- figurations, then configure the fpgas using a daisy chain, as shown in figure 64 . use slave serial mode (m[2:0] = <1:1:1>) for all fpgas in the daisy-chain. after the lead fpga is filled with it s configuration data, the lead fpga passes configuration data via its dout output pin to the next fpga on the falling cclk edge. figure 63: slave serial configuration +2.5v tdi tdo tm s tck vccint vccaux +2.5v vcco_2 init_b prog_b done gnd +1.2v h s wap vcco_0 p vcco_0 4.7k spartan- 3 e fpga +2.5v jtag prog_b recommend open-drain driver tdi tm s tck tdo m2 m1 ?1? ?1? m0 ?1? dout 33 0 din cclk v slave serial mode 4.7k v clock s erial_out prog_b init_b done v vcc gnd config u r a tion memory s o u rce ? intern a l memory ? di s k drive ? over network ? over rf link intelligent download ho s t ? microcontroller ? proce ss or ? te s ter ? comp u ter d s3 12-2_54_0 8 2009 p v functional description 100 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r ta bl e 6 6 : slave serial mode connections pin name fpga direction description during configuration after configuration hswap input user i/o pull-up control . when low during configuration, enables pull-up resistors in all i/o pins to respective i/o bank v cco input. 0: pull-up during configuration 1: no pull-ups drive at valid logic level throughout configuration. user i/o m[2:0] input mode select . selects the fpga configuration mode. see design considerations for the hswap, m[2:0], and vs[2:0] pins . m2 = 1, m1 = 1, m0 = 1 sampled when init_b goes high. user i/o din input data input . serial data provided by host. fpga captures data on rising cclk edge. user i/o cclk input configuration clock . if cclk pcb trace is long or has multiple connections, terminate this output to maintain signal integrity. see cclk design considerations . external clock. user i/o init_b open-drain bidirectional i/o initialization indicator . active low. goes low at start of configuration during initialization memory clearing process. released at end of memory clearing, when mode select pins are sampled. in daisy-chain applications, this signal requires an external 4.7 k pull-up resistor to vcco_2. active during configuration. if crc error detected during configuration, fpga drives init_b low. user i/o. if unused in the application, drive init_b high. done open-drain bidirectional i/o fpga configuration done . low during configuration. goes high when fpga successfully completes configuration. requires external 330 pull-up resistor to 2.5v. low indicates that the fpga is not yet configured. pulled high via external pull-up. when high, indicates that the fpga successfully configured. prog_b input program fpga . active low. when asserted low for 500 ns or longer, forces the fpga to restart its configuration process by clearing configuration memory and resetting the done and init_b pins once prog_b returns high. recommend external 4.7 k pull-up resistor to 2.5v. internal pull-up value may be weaker (see ta bl e 7 8 ). if driving externally with a 3.3v output, use an open-drain or open-collector driver or use a current limiting series resistor. must be high to allow configuration to start. drive prog_b low and release to reprogram fpga. functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 101 product specification r jtag mode for additional information, refer to the ? jtag configuration mode and boundary-scan ? chapter in ug332 . the spartan-3e fpga has a dedicated four-wire ieee 1149.1/1532 jtag port that is always available any time the fpga is powered and regardless of the mode pin settings. however, when the fpga mode pins are set for jtag mode (m[2:0] = <1:0:1>), the fpga waits to be configured via the jtag port after a power-on event or when prog_b is asserted. selecting the jtag mode simply disables the other configuration modes. no other pins are required as part of the configuration interface. figure 65 illustrates a jtag-only configuration interface. the jtag interface is easily cascaded to any number of fpgas by connecting the tdo output of one device to the tdi input of the next device in the chain. the tdo output of the last device in the chain loops back to the port connector. design note if using software versions prior to ise 9.1.01i, avoid config- uring the fpga using jtag if... ? the mode pins are set for a master mode ? the attached master mode prom contains a valid fpga configuration bitstream. the fpga bitstream may be corrupted and the done pin may go high. the following answer record contains addi- tional information. http://www.xilinx.com/supp ort/answers/22255.htm figure 64: daisy-chaining using slave serial mode +2.5v tdi tdo tm s tck vccint vccaux +2.5v vcco_2 init_b prog_b done gnd +1.2v h s wap vcco_0 p tdi tdo tm s tck vccint vccaux din dout vcco_2 init_b prog_b done gnd +1.2v m2 m1 ?1? ?1? m0 h s wap vcco_0 p vcco_2 +2.5v ?1? vcco_0 4.7k +2.5v jtag cclk init_b done prog_b tck tm s prog_b recommend open-drain driver vcco_0 tdi tm s tck tdo m2 m1 ?1? ?1? m0 ?1? dout spartan- 3 e fpga spartan- 3 e fpga dout cclk 33 0 din cclk v slave serial mode slave serial mode 4.7k v clock s erial_out prog_b init_b done v vcc gnd config u r a tion memory s o u rce ? intern a l memory ? di s k drive ? over network ? over rf link intelligent download ho s t ? microcontroller ? proce ss or ? te s ter ? comp u ter d s3 12-2_55_0 8 2009 functional description 102 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r voltage compatibility the 2.5v v ccaux supply powers the jtag interface. all of the user i/os are separately powered by their respective vcco_# supplies. when connecting the spartan-3e jtag port to a 3.3v inter- face, the jtag input pins must be current-limited to 10 ma or less using series resistors. similarly, the tdo pin is a cmos output powered from +2.5v. the tdo output can directly drive a 3.3v input but with reduced noise immunity. see x app453 : the 3.3v configuration of spartan-3 fpgas for additional information. jtag device id each spartan-3e fpga array type has a 32-bit device-spe- cific jtag device identifier as shown in ta bl e 6 7 . the lower 28 bits represent the device vendor (xilinx) and device iden- tifer. the upper four bits, ignored by most tools, represent the revision level of the silicon mounted on the printed circuit board. ta bl e 6 7 associates the revision code with a specific stepping level. jtag user id the spartan-3e jtag interface also provides the option to store a 32-bit user id, loaded during configuration. the user id value is specified via the userid configuration bit- stream option, shown in table 69, page 109 . using jtag interface to communicate to a configured fpga design after the fpga is configured, using any of the available modes, the jtag interface offers a possible communica- tions channel to internal fpga logic. the bscan_spartan3 design primitive provides two private jtag instructions to create an internal boundary scan chain. figure 65: jtag configuration mode tdi tdo tm s tck vccint vccaux +2.5v vcco_2 prog_b done gnd +1.2v h s wap vcco_0 p vcco_0 spartan- 3 e fpga +2.5v jtag tck tm s spartan- 3 e fpga tdi tm s tck tdo m2 m1 ?1? ?0? m0 ?1? jtag mode vcco_2 tdi tdo tm s tck vccint vccaux +2.5v vcco_2 prog_b done gnd +1.2v h s wap vcco_0 p vcco_0 m2 m1 ?1? ?0? m0 ?1? jtag mode vcco_2 d s3 12-2_56_0 8 2009 ta bl e 6 7 : spartan-3e jtag device identifiers spartan-3e fpga 4-bit revision code 28-bit vendor/device identifier step 0 step 1 xc3s100e 0x0 0x1 0x1c 10 093 xc3s250e 0x0 0x1 0x1c 1a 093 xc3s500e 0x0 0x2 0x4 0x1c 22 093 xc3s1200e 0x0 0x1 0x2 0x1c 2e 093 xc3s1600e 0x0 0x1 0x2 0x1c 3a 093 functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 103 product specification r maximum bitstream size for daisy-chains the maximum bitstream length supported by spartan-3e fpgas in serial daisy-chains is 4,294,967,264 bits (4 gbits), roughly equivalent to a daisy-chain with 720 xc3s1600e fpgas. this is a limit only for serial daisy-chains where configurat ion data is passed via the fpga?s dout pin. there is no such limit for jtag chains. configuration sequence for additional information including i/o behavior before and during configuration, refer to the ? sequence of events ? chapter in ug332 . the spartan-3e configuration process is three-stage pro- cess that begins after the fpga powers on (a por event) or after the prog_b input is asserted. power-on reset (por) occurs after the v ccint , v ccaux , and the v cco bank 2 supplies reach their respective input threshold levels. after either a por or prog_b event, the three-stage con- figuration process begins. 1. the fpga clears (initializes) the internal configuration memory. 2. configuration data is loaded into the internal memory. 3. the user-application is activated by a start-up process. figure 66 is a generalized block diagram of the spartan-3e configuration logic, showing the interaction of different device inputs and bitstream generator (bitgen) options. a flow diagram for the configuration sequence of the serial and parallel modes appears in figure 67 . figure 68 shows the boundary-scan or jtag configuration sequence. initialization configuration automatically begins after power-on or after asserting the fpga prog_b pin, unless delayed using the fpga?s init_b pin. the fpga holds the open-drain init_b signal low while it clears its internal configuration memory. externally holding the init_b pin low forces the configura- tion sequencer to wait until init_b again goes high. the fpga signals when the memory-clearing phase is complete by releasing the open-drain init_b pin, allowing the pin to go high via the external pull-up resistor to vcco_2. loading configuration data after initialization, configurat ion data is written to the fpga?s internal memory. the fpga holds the global set/reset (gsr) signal active throughout configuration, holding all fpga flip-flops in a reset state. the fpga sig- nals when the entire configuration process completes by releasing the done pin, allowing it to go high. the fpga configuration sequence can also be initiated by asserting prog_b. once released, the fpga begins clearing its internal configuration memory, and progresses through the remainder of the configuration process. functional description 104 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r figure 66: generalized spartan-3e fpga c onfiguration logic block diagram DS312-2_57_102605 v cco_2 v cco2t v cci n t v cci n tt v ccaux v ccauxt prog_b cclk tck internal oscillator m1 m2 configrate reset reset e n able reset e n able do n e gts gsr gwe do n e_cycle gwe_cycle gts_cycle dcms_locked startupclk 0 0 1 1 initialization configuration startup user_clock i n ter n al_co n figuratio n _clock jtag_clock clear internal cmos configuration latches load application data into cmos configuration latches enable application logic and i/o pins i n it_b e n able configuration error detection (crc checker) e n able crc error power_good option = bitstream generator (bitgen) option dcm in user application locked startup_wait=true lck_cycle drivedone donepipe option = design attribute all dcms wait do n edo n e cleari n g_memory glitch filter do n e wait force all i/os hi-z hold all storage elements reset disable write operations to storage elements gts_i n gsr_i n user user * * * * these connections are available via the startup_sparta n 3e library primitive. e n e n power on reset (por) functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 105 product specification r figure 67: general configuration process sa mple mode pin s no no no ye s ye s ye s cle a r config u r a tion memory power-on s et prog_b low a fter power-on ye s no crc correct? ye s no reconfig u re? lo a d config u r a tion d a t a fr a me s init_b goe s low. a b ort s t a rt-up s t a rt-up s eq u ence u s er mode init_ b = high? prog_b = low d s3 12-2_5 8 _051706 v ccint >1v a nd v ccaux > 2v a nd v cco b a nk 2 > 1v m[2:0] and vs[2:0] pins are sampled on init_b rising edge done pin goes high, signaling end of configuration functional description 106 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r figure 68: boundary-scan configuration flow diagram sa mple mode pin s (jtag port b ecome s a v a il ab le) cle a r config u r a tion memory no no no ye s ye s ye s ye s no no power-on crc correct? lo a d cfg_in in s tr u ction reconfig u re? lo a d j s ta rt in s tr u ction s ynchrono us tap re s et (clock five 1' s on tm s ) s t a rt-up s eq u ence u s er mode init_b = high? prog_b = low lo a d jprog in s tr u ction ye s lo a d config u r a tion d a t a fr a me s v ccint >1v a nd v ccaux > 2v a nd v cco b a nk 2 > 1v init_b goe s low. a b ort s t a rt-up s et prog_b low a fter power-on d s3 12-2_59_051706 functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 107 product specification r start-up at the end of configuration, the fpga automatically pulses the global set/reset (gsr) signal, placing all flip-flops in a known state. after configuration completes, the fpga switches over to the user application loaded into the fpga. the sequence and timing of how the fpga switches over is programmable as is the clock source controlling the sequence. the default start-up sequence appears in figure 69 , where the global three-state signal (gts) is released one clock cycle after done goes high. this sequence allows the done signal to enable or disable any external logic used during configuration before the user application in the fpga starts driving output signals. one clock cycle later, the glo- bal write enable (gwe) signal is released. this allows sig- nals to propagate within the fpga before any clocked storage elements such as flip-flops and block rom are enabled. the function of the dual-purpose i/o pins , such as m[2:0], vs[2:0], hswap, and a[23:0] , also changes when the done pin goes high. when done is high, these pins become user i/os. like all user-i/o pins, gts controls when the dual-purpose pins can drive out. the relative timing of configuration events is programmed via the bitstream generator (b itgen) options in the xilinx development software. for example, the gts and gwe events can be programmed to wait for all the done pins to high on all the devices in a mu ltiple-fpga daisy-chain, forc- ing the fpgas to start synchronously. similarly, the start-up sequence can be paused at any stage, waiting for selected dcms to lock to their respective input clock signals. see also stabilizing dcm clocks before user mode . by default, the start-up sequence is synchronized to cclk. alternatively, the start-up sequence can be synchronized to a user-specified clock from within the fpga application using the startup_spartan3e library primitive and by setting the startupclk bitstream generator option. the fpga application can optionally assert the gsr and gts signals via the startup_spartan3e primitive. for jtag configuration, the start-up sequence can be synchronized to the tck clock input. figure 69: default start-up sequence start-up clock default cycles s ync-to-done 01 23 45 67 01 done high 23 45 67 phase start-up clock phase done gts gwe done gts gwe DS312-2_60_022305 functional description 108 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r readback fpga configuration data can be read back using either the slave parallel or jtag mode. this function is disabled if the bitstream generator security option is set to either level1 or level2 . along with the configuration data, it is possible to read back the contents of all registers and distributed ram. to synchronously control when register values are captured for readback, use the capture_spartan3 library primi- tive, which applies for both spartan-3 and spartan-3e fpga families. the readback feature is available in most spartan-3e fpga product options, as indicated in ta bl e 6 8 . the read- back feature is not available in the xc3s1200e and xc3s1600e fpgas when using the -4 speed grade in the commercial temperature grade. similarly, block ram read- back support is not available in the -4 speed grade, com- mercial temperature devices. if readback is required in an xc3s1200e or xc3s1600e fpga, or if block ram read- back is required on any spartan-3e fpga, upgrade to either the industrial temperature grade version or the -5 speed grade. the xilinx impact programmin g software uses the read- back feature for its optional verify and readback opera- tions. the xilinx chipscope? software presently does not use readback but may in future updates. table 68: readback support in spartan-3e fpgas temperature range commercial industrial speed grade -4 -5 -4 block ram readback all spartan-3e fpgas no yes yes general readback (registers, distributed ram) xc3s100e yes yes yes xc3s250e yes yes yes xc3s500e yes yes yes xc3s1200e no yes yes xc3s1600e no yes yes functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 109 product specification r bitstream generator (bitgen) options for additional information, refer to the ? configuration bit- stream generator (bitgen) settings ? chapter in ug332 . various spartan-3e fpga functions are controlled by spe- cific bits in the configuration bitstream image. these values are specified when creating the bitstream image with the bitstream generator (bitgen) software. ta b l e 6 9 provides a list of all bitgen options for spartan-3e fpgas. ta bl e 6 9 : spartan-3e fpga bitstream generator (bitgen) options option name pins/function affected values ( default ) description configrate cclk, configuration 1 , 3, 6, 12, 25, 50 sets the approximate frequency, in mhz, of the internal oscillator using for master serial, spi, and bpi configuration modes. the in ternal oscillator powers up at its lowest frequency, and the new setting is loaded as pa rt of the configuration bitstream. the software default value is 1 (~1.5 mhz) starting with ise 8.1, service pack 1. startupclk configuration, startup cclk default. the cclk signal (internally or exter nally generated) controls the startup sequence when the fpga transitions from configuration mode to the user mode. see start-up . userclk a clock signal from within the fpga app lication controls the startup sequence when the fpga transitions from configur ation mode to the user mode. see start-up . the fpga application supplies the user clock on the clk pin on the startup_spartan3e primitive. jtag the jtag tck input controls the startu p sequence when the fpga transitions from the configuration mode to the user mode. see start-up . unusedpin unused i/o pins pulldown default. all unused i/o pins and input-only pins have a pull-down resistor to gnd. pullup all unused i/o pins and input-only pins have a pull-up resistor to the vcco_# supply for its associated i/o bank. pullnone all unused i/o pins and input-only pins are left floating (hi-z, high-impedance, three-state). use external pull-up or pull-down resistors or logic to apply a valid signal level. done_cycle done pin, configuration startup 1, 2, 3, 4 , 5, 6 selects the configuration startup phase t hat activates the fpga?s done pin. see start-up . gwe_cycle all flip-flops, lut rams, and srl16 shift registers, block ram, configuration startup 1, 2, 3, 4, 5, 6 selects the configuration startup phase that asserts the internal write-enable signal to all flip-flops, lut rams and shift registers (srl16). it also enables block ram read and write operations. see start-up . done waits for the done pin input to go hi gh before asserting the internal write-enable signal to all flip-flops, lut rams and sh ift registers (srl16). block ram read and write operations are enabled at this time. keep retains the current gwe_cycle setting for partial reconfiguration applications. gts_cycle all i/o pins, configuration 1, 2, 3, 4, 5 , 6 selects the configuration start up phase that releases the in ternal three-state control, holding all i/o buffers in high-impedance (hi-z). output buffers actively drive, if so configured, after this point. see start-up . done waits for the done pin input to go high before releasing the internal three-state control, holding all i/o buffers in high-impedance (hi-z). output buffers actively drive, if so configured, after this point. keep retains the current gts_cycle setting for partial reconfiguration applications. lck_cycle dcms, configuration startup nowait the fpga does not wait for selected dcms to lock before completing configuration. 0, 1, 2, 3, 4, 5, 6 if one or more dcms in the design have the startup_wait attribute set to true, the fpga waits for such dcms to acquire their respective input clock and assert their locked output. this setting selects the c onfiguration startup phase where the fpga waits for the dcms to lock. functional description 110 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r donepin done pin pullup internally connects a pull-up resistor between done pin and v ccaux . an external 330 pull-up resistor to v ccaux is still recommended. pullnone no internal pull-up resistor on done pin. an external 330 pull-up resistor to v ccaux is required. drivedone done pin no when configuration completes, the done pin stops driving low and relies on an external 330 pull-up resistor to v ccaux for a valid logic high. yes when configuration completes, the done pin actively drives high. when using this option, an external pull-up resistor is no lo nger required. only one device in an fpga daisy-chain should use this setting. donepipe done pin no the input path from done pin input back to the startup sequencer is not pipelined. yes this option adds a pipeline register stage between the done pin input and the startup sequencer. used for high-speed daisy-chain configurations when done cannot rise in a single cclk cycle. releases gwe and gt s signals on the fi rst rising edge of startupclk after the done pin input goes high. progpin prog_b pin pullup internally connects a pull-up resistor or between prog_b pin and v ccaux . an external 4.7 k pull-up resistor to v ccaux is still recommended since the internal pull-up value may be weaker (see ta b l e 7 8 ). pullnone no internal pull-up resistor on prog_b pin. an external 4.7 k pull-up resistor to v ccaux is required. tckpin jtag tck pin pullup internally connects a pull-up resistor between jtag tck pin and v ccaux . pulldown internally connects a pull-down resistor between jtag tck pin and gnd. pullnone no internal pull-up resistor on jtag tck pin. tdipin jtag tdi pin pullup internally connects a pull-up resistor between jtag tdi pin and v ccaux . pulldown internally connects a pull-down resistor between jtag tdi pin and gnd. pullnone no internal pull-up resistor on jtag tdi pin. tdopin jtag tdo pin pullup internally connects a pull-up resistor between jtag tdo pin and v ccaux . pulldown internally connects a pull-down resistor between jtag tdo pin and gnd. pullnone no internal pull-up resistor on jtag tdo pin. tmspin jtag tms pin pullup internally connects a pull-up resistor between jtag tms pin and v ccaux . pulldown internally connects a pull-down resistor between jtag tms pin and gnd. pullnone no internal pull-up resistor on jtag tms pin. userid jtag user id register user string the 32-bit jtag user id register value is loaded during configuration. the default value is all ones, 0xffff_ffff hexadecimal. to specify another value, enter an 8-character hexadecimal value. security jtag, selectmap, readback, partial reconfiguration none readback and limited partial reconfiguration are available via the jtag port or via the selectmap interface, if the persist option is set to yes . level1 readback function is disabled. limited par tial reconfiguration is still available via the jtag port or via the selectmap interface, if the persist option is set to yes . level2 readback function is disabled. limi ted partial reconfiguration is disabled. ta bl e 6 9 : spartan-3e fpga bitstream generator (bitgen) options (continued) option name pins/function affected values ( default ) description functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 111 product specification r powering spartan-3e fpgas for additional information, refer to the ? powering spartan-3 generation fpgas ? chapter in ug331 . voltage supplies like spartan-3 fpgas, spartan-3e fpgas have multiple voltage supply inputs, as shown in ta bl e 7 0 . there are two supply inputs for internal logic functions, v ccint and v ccaux . each of the four i/o banks has a separate v cco supply input that powers the output buffers within the asso- ciated i/o bank. all of the v cco connections to a specific i/o bank must be connected and must connect to the same voltage. in a 3.3v-only application, all four v cco supplies connect to 3.3v. however, spartan-3e fpgas provide the ability to bridge between different i/o voltages and standards by applying different voltages to the v cco inputs of different banks. refer to i/o banking rules for which i/o standards can be intermixed within a single i/o bank. each i/o bank also has an separate, optional input voltage reference supply, called v ref . if the i/o bank includes an i/o standard that requires a voltage reference such as hstl or sstl, then all v ref pins within the i/o bank must be con- nected to the same voltage. crc configuration enable default. enable crc checking on the fpga bi tstream. if error detected, fpga asserts init_b low and done pin stays low. disable turn off crc checking. persist selectmap interface pins, bpi mode, slave mode, configuration no all bpi and slave mode configuration pins ar e available as user-i/o after configuration. yes this option is required for readback and partial reconfiguration using the selectmap interface. the selectmap interface pins (see slave parallel mode ) are reserved after configuration and are not available as user-i/o. ta bl e 6 9 : spartan-3e fpga bitstream generator (bitgen) options (continued) option name pins/function affected values ( default ) description ta bl e 7 0 : spartan-3e voltage supplies supply input description nominal supply voltage v ccint internal core supply voltage. supplies all internal logic functions, such as clbs, block ram, and multipliers. input to power-on reset (por) circuit. 1.2v v ccaux auxiliary supply voltage. supplies digital clock managers ( dcms), differential drivers, dedicated configuration pins, jtag interface. input to power-on reset (por) circuit. 2.5v vcco_0 supplies the output buffers in i/o bank 0, the bank along the top edge of the fpga. selectable, 3.3v, 2.5v, 1.8, 1.5v, or 1.2v vcco_1 supplies the output buffers in i/o bank 1, the bank along the right edge of the fpga. in byte-wide peripheral interface (bpi) parallel flash mode , connects to the same voltage as the flash prom. selectable, 3.3v, 2.5v, 1.8, 1.5v, or 1.2v vcco_2 supplies the output buffers in i/o bank 2, the bank along the bottom edge of the fpga. connects to the same voltage as the fpga configuration source. input to power-on reset (por) circuit. selectable, 3.3v, 2.5v, 1.8, 1.5v, or 1.2v vcco_3 supplies the output buffers in i/o bank 3, the bank along the left edge of the fpga. selectable, 3.3v, 2.5v, 1.8, 1.5v, or 1.2v functional description 112 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r voltage regulators various power supply manufact urers offer complete power solutions for xilinx fpgas in cluding some with integrated three-rail regulators specifically designed for spartan-3 and spartan-3e fpgas. the x ilinx power corner website pro- vides links to vendor solution guides and xilinx power esti- mation and analysis tools. power distribution s ystem (pds) design and decoupling/b ypass capacitors good power distribution system (pds) design is important for all fpga designs, but especially so for high performance applications, greater than 100 mhz. proper design results in better overall performance, lower clock and dcm jitter, and a generally more robust system. before designing the printed circuit board (pcb) for the fpga design, please review xapp623 : power distribution system (pds) design: using bypass/decoupling capacitors . power-on behavior for additional power-on behavior information, including i/o behavior before and during configuration, refer to the ? sequence of events ? chapter in ug332 . spartan-3e fpgas have a built-in power-on reset (por) circuit that monitors the three power rails required to suc- cessfully configure the fpga. at power-up, the por circuit holds the fpga in a reset state until the v ccint , v ccaux , and v cco bank 2 supplies reach their respective input threshold levels (see ta b l e 7 4 in module 3). after all three supplies reach their respective thresholds, the por reset is released and the fpga begins its configuration process. supply sequencing because the three fpga supply inputs must be valid to release the por reset and can be supplied in any order, there are no fpga-specific voltage sequencing require- ments. applying the fpga?s v ccaux supply before the v ccint supply uses the least i ccint current. although the fpga has no specific voltage sequence requirements, be sure to consider any potential sequencing requirement of the configuration device attached to the fpga, such as an spi serial flash prom, a parallel nor flash prom, or a microcontroller. for example, flash proms have a minimum time requirement before the prom can be selected and this must be considered if the 3.3v supply is the last in the sequence. see power-on pre- cautions if 3.3v supply is last in sequence for more details. when all three supplies are valid, the minimum current required to power-on the fpga equals the worst-case qui- escent current, specified in ta b l e 7 9 . spartan-3e fpgas do not require power-on surge (pos) current to successfully configure. surplus i ccint if v ccint applied before v ccaux if the v ccint supply is applied before the v ccaux supply, the fpga might draw a surplus i ccint current in addition to the i ccint quiescent current le vels specified in ta b l e 7 9 , page 121 . the momentary additional i ccint surplus current might be a few hundred millia mperes under nominal condi- tions, significantly less than the instantaneous current con- sumed by the bypass capacitors at power-on. however, the surplus current immediately disappears when the v ccaux supply is applied, and, in response, the fpga?s i ccint qui- escent current demand drops to the levels specified in ta b l e 7 9 . the fpga does not use or require the surplus current to successfully power-on and configure. if applying v ccint before v ccaux , ensure that the regulator does not have a foldback feature that could inadvertently shut down in the presence of the surplus current. configuration data re tention, brown-out the fpga?s configuration data is stored in robust cmos configuration latches. the data in these latches is retained even when the voltages drop to the minimum levels neces- sary to preserve ram contents, as specified in ta bl e 7 6 . if, after configuration, the v ccaux or v ccint supply drops below its data retention voltage, the current device configu- ration must be cleared using one of the following methods: ? force the v ccaux or v ccint supply voltage below the minimum power on reset (por) voltage threshold ( ta bl e 7 4 ). ? assert prog_b low. the por circuit does not monitor the vcco_2 supply after configuration. consequently, dropping the vcco_2 voltage does not reset the device by triggering a power-on reset (por) event. no internal charge pu mps or free-running oscillators some system applications are sensitive to sources of ana- log noise. spartan-3e fpga circ uitry is fully static and does not employ internal charge pumps. the cclk configuration clock is active during the fpga configuration process. after configuration completes, the cclk oscillator is automatica lly disabled unless the bit- stream generator (bitgen) option persist =yes . functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 113 product specification r production stepping the spartan-3e fpga family uses production stepping to indicate improved capabilities or enhanced features. stepping 1 is, by definition, a functional superset of step- ping 0. furthermore, configuration bitstreams generated for stepping 0 are compatible with stepping 1. designs operating on the stepping 0 devices perform simi- larly on a stepping 1 device. differences between steppings ta b l e 7 1 summarizes the feature and performance differ- ences between stepping 0 devices and stepping 1 devices. ordering a later stepping -5c and -4i devices, and -4c devices (with date codes 0901 (2009) and later) always support the stepping 1 feature set independent of the stepping code. optionally, to order only stepping 1 for the -4c devices, append an ?s1? suffix to the standard ordering code, where ?1? is the stepping number, as indicated in ta b l e 7 2 . ta bl e 7 1 : differences between spartan-3e production stepping levels stepping 0 stepping 1 production status production from 2005 to 2007 production starting march 2006 speed grade and operating conditions -4c only -4c, -4i, -5c jtag id code different revision fields. see ta bl e 6 7 . dcm dll maximum input frequency 90 mhz (200 mhz for xc3s1200e) 240 mhz (?4 speed grade) 275 mhz (?5 speed grade) dcm dfs output frequency range(s) split ranges at 5 ? 90 mhz and 220 ? 307 mhz (single range 5 ? 307 mhz for xc3s1200e) continuous range: 5 ? 311 mhz (?4) 5 ? 333 mhz (?5) supports multi-fpga daisy-chain configurations from spi flash no, single fpga only yes jtag configuration supported when fpga in bpi mode with a valid image in the attached parallel nor flash prom no (1) ye s jtag extest, intest, sample support y es: xc3s100e, xc3s250e, xc3s500e no (2) : xc3s1200e, xc3s1600e ye s all devices power sequencing when using hswap pull-up requires v ccint before v ccaux any sequence pci compliance no yes notes: 1. workarounds exist. see stepping 0 limitations when reprogramming via jtag if fpga set for bpi configuration . 2. jtag bypass and jtag configuration are supported table 72: spartan-3e optional stepping ordering stepping number suffix code status 0 none production 1 s1 production functional description 114 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r software version requirements production spartan-3e applications must be processed using the xilinx ise 8.1i, service pack 3 or later develop- ment software, using the v1.21 or later speed files. the ise 8.1i software implements critical bitstream generator updates. for additional information on spartan-3e development soft- ware and known issues, see the following answer record: ? xilinx answer #22253 http://www.xilinx.com/supp ort/answers/22253.htm functional description DS312-2 (v3.8) august 26, 2009 www.xilinx.com 115 product specification r revision history the following table shows the revision history for this document. date version revision 03/01/05 1.0 initial xilinx release. 03/21/05 1.1 updated figure 45 . modified title on ta b l e 3 9 and ta bl e 4 5 . 11/23/05 2.0 updated values of on-chip differential termination resistors. updated ta bl e 7 . updated configuration bitstream sizes for xc3s250e through xc3s1600e in ta b l e 4 5 , ta b l e 5 1 , ta b l e 5 7 , and ta b l e 6 0 . added dll performance differences between steppings . added stepping 0 limitations when reprogra mming via jtag if fpga set for bpi configuration . added stepping 0 limitations when daisy-chaining in spi configuration mode. added multiplier/block ram interaction section. updated digital clock managers (dcms) section, especially phase shifter (ps) portion. corrected and enhanced the clock infrastructure diagram in figure 45 and ta b l e 4 1 . added cclk design considerations section. added design considerations for the hswap, m[2:0], and vs[2:0] pins section. added spansion, winbond, and macronix to list of spi flash vendors in ta b l e 5 3 and ta bl e 5 6 . clarified that spi mode config uration supports atmel ?c?- and ?d?-series dataflash. updated the programming support section for spi flash proms. added power-on precautions if prom supply is last in sequence , compatible flash families , and bpi mode interaction with right and bottom edge global clock inputs sections to bpi configuration mode topic. updated and amplified powering spartan-3e fpgas section. added production stepping section. 03/22/06 3.0 upgraded data sheet status to preliminary. updated input delay functions and figure 6 . added clarification that input-only pins also have pull-up and pull-down resistors . added design note about address setup and hold requirements to block ram . added warning message about software differences between ise 8.1i, service pack 3 and earlier software to fixed phase shift mode and variable phase shift mode . added message about using gclk1 in dll clock input connections and clock inputs . updated figure 45 . added additional information on hswap behavior to pin behavior during configuration . highlighted which pins have configuration pull-up resistors unaffected by hswap in ta b l e 4 6 . updated bitstream image sizes for the xc3s1200e and xc3s1600e in ta b l e 4 5 , ta bl e 5 1 , ta bl e 5 7 , and ta bl e 6 0 . clarified that ?b?-seri es atmel dataflash spi proms can be used in commercial temperature range applications in ta bl e 5 3 and figure 54 . updated figure 56 . updated dynamically loading multiple configuration images using multiboot option section. added design note about bpi daisy-chaining software support to bpi daisy-chaining section. updated jtag revision codes in ta b l e 6 7 . added no internal charge pumps or free-running oscillators . updated information on production stepping differences in ta b l e 7 1 . updated software version requirements . 04/10/06 3.1 updated jtag user id information. clarified note 1, figure 5 . clarified that figure 45 shows electrical connectivity and corrected left- and right-edge dcm coordinates. updated ta b l e 3 0 , ta bl e 3 1 , and ta b l e 3 2 to show the specific clock line driven by the associated bufgmux primitive. corrected the coordinate locations for the associated bufgmux primitives in ta b l e 3 1 and ta bl e 3 2 . updated ta b l e 4 1 to show that the i0-input is the preferred connection to a bufgmux. 05/19/06 3.2 made further clarifying changes to figure 46 , showing both direct inputs to bufgmux primitives and to dcms. added atmel at45dbxxxd-series dataflash serial proms to ta b l e 5 3 . added details that intermediate fpgas in a bpi-mode, multi-fpga configuration daisy-chain must be from either the spartan- 3e or the virtex-5 fpga families (see bpi daisy-chaining ). added using jtag interface to communicate to a configured fpga design . minor updates to figure 67 and figure 68 . clarified which spartan-3e fpga product options support the readback feature, shown in ta bl e 6 8 . functional description 116 www.xilinx.com DS312-2 (v3.8) august 26, 2009 product specification r 05/30/06 3.2.1 corrected various typos and incorrect links. 10/02/06 3.3 clarified that the block ram readback feature is available either on the -5 speed grade or the industrial temperature range. 11/09/06 3.4 updated the description of the input delay functions . the oddr2 flip-flop with c0 or c1 alignment is no longer supported. updated figure 5 . updated ta b l e 6 for improved pci input voltage tolerance. replaced missing text in clock buffers/multiplexers . updated spi flash devices in ta bl e 5 3 . updated parallel nor flash devices in ta bl e 6 1 . direct, spi flash in-system programming support was added beginning with ise 8.1i impact software for stmicro and atmel spi proms. updated ta bl e 7 1 and ta b l e 7 2 as stepping 1 is in full production. freshened various hyper links. promoted module 2 to production status. 03/16/07 3.5 added information about new spartan-3 generation user guides ( design documentation available ). added cross-references to ug331 : spartan-3 generation fpga user guide and to ug332 : spartan-3 generation configuration user guide . added note about possible jtag configuration issues when the fpga mode pins are set for master mode and using software prior to ise 9.1.01i ( jtag mode ). removed a few lingering references to ?weak? pull-up resistors, including in figure 12 . removed vestigial references regarding the ldc[2:0] and hdc pins during slave parallel mode configuration. these pins are not used in this configuration mode. 05/29/07 3.6 added information about hswap and pci differences between steppings to ta bl e 7 1 . removed ?performance differences between global buffers? to match improved specs in module 3. updated prog_b pulse width descriptions to match specification in module 3. 04/18/08 3.7 corrected figure 6 to show six taps and updated associated text. added note for recommended pull-up on done in ta bl e 5 5 and elsewhere. added a caution regarding persist of pins a20-a23. updated stepping description in ta bl e 7 1 to note that only stepping 1 is in productio n today. updated links. 08/26/09 3.8 added a frequency limitation to equation 6, page 57 . added a new equation 7, page 57 with a frequency limitation. added a spread spectrum , page 58 paragraph. added ta bl e 4 2 , page 62 . updated a flash vendor name in table 61, page 90 . removed the < symbol from the flash read access times in table 62, page 90 . revised the first paragraph in configuration sequence , page 103 . revised the first paragraph in power-on behavior , page 112 . revised the second paragraph in production stepping , page 113 . revised the first paragraph in ordering a later stepping , page 113 . date version revision DS312-3 (v3.8) august 26, 2009 www.xilinx.com 117 product specification ? 2005?2009 xilinx, inc. xilinx, the xilinx logo, virtex, spartan, ise, and other designated brands included herein are tradema rks of xilinx in the united states and other coun- tries. all other trademarks are the property of their respective owners. dc electrical characteristics in this section, specifications may be designated as advance, preliminary, or production. these terms are defined as follows: advance: initial estimates are based on simulation, early characterization, and/or extrapolation from the characteris- tics of other familie s. values are subject to change. use as estimates, not for production. preliminary: based on characterization. further changes are not expected. production: these specifications are approved once the silicon has been characterize d over numer ous production lots. parameter values are considered stable with no future changes expected. all parameter limits are represen tative of worst-case supply voltage and junction temperature conditions. unless other- wise noted, the published parameter values apply to all spartan ? -3e devices. ac and dc characteristics are specified using the same numbers for both commercial and industrial grades. absolute maximum ratings stresses beyond those listed under ta bl e 7 3 : absolute maximum ratings may cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the recommended operating conditions is not implied. exposure to absolute maximum conditions for extended periods of time adverse ly affects device reliability. 162 spartan-3e fpga family: dc and switching characteristics DS312-3 (v3.8) august 26, 2009 0 product specification r ta bl e 7 3 : absolute maximum ratings symbol description conditions min max units v ccint internal supply voltage ?0.5 1.32 v v ccaux auxiliary supply voltage ?0.5 3.00 v v cco output driver supply voltage ?0.5 3.75 v v ref input reference voltage ?0.5 v cco +0.5 (1) v v in (1,2,3,4) voltage applied to all user i/o pins and dual-purpose pins driver in a high-impedance state commercial ?0.95 4.4 v industrial ?0.85 4.3 v voltage applied to all dedicated pins all temp. ranges ?0.5 v ccaux +0.5 (3) v i ik input clamp current per i/o pin ?0.5 v < v in < (v cco + 0.5 v) ? 100 ma v esd electrostatic discharge voltage human body model ? 2000 v charged device model ? 500 v machine model ? 200 v t j junction temperature ?125c t stg storage temperature ?65 150 c notes: 1. each of the user i/o and dual-purpose pins is associated with one of the four banks? v cco rails. keeping v in within 500 mv of the associated v cco rails or ground rail ensures that the internal diode junctions do not turn on. ta bl e 7 7 specifies the v cco range used to evaluate the maximum v in voltage. 2. input voltages outside the -0.5v to v cco + 0.5v (or v ccaux + 0.5v) voltage range are permissible provided that the i ik input diode clamp diode rating is met and no more than 100 pins exceed the range simultaneously. prolonged exposure to such current may compromis e device reliability. a sustained current of 10 ma will not compromise device reliability. see xapp459 , eliminating i/o coupling effects when interfacing large-swing single-ended signals to user i/o pins on spartan-3 generation fpgas for more details. 3. all dedicated pins (prog_b, done, tck, td i, tdo, and tms) draw power from the v ccaux rail (2.5v). meeting the v in max limit ensures that the internal diode junctions that exist between each of these pins and the v ccaux rail do not turn on. ta b l e 7 7 specifies the v ccaux range used to evaluate the maximum v in voltage. as long as the v in max specification is met, oxide stress is not possible. 4. see xapp459 , "eliminating i/o coupling effects when interfacing large-swing single-ended signals to user i/o pins." 5. for soldering guidelines, see ug112 : device packaging and thermal characteristics and xapp427 : implementation and solder reflow guidelines for pb-free packages . dc and switching characteristics 118 www.xilinx.com DS312-3 (v3.8) august 26, 2009 product specification r power supply specifications ta bl e 7 4 : supply voltage thresholds for power-on reset symbol description min max units v ccintt threshold for the v ccint supply 0.4 1.0 v v ccauxt threshold for the v ccaux supply 0.8 2.0 v v cco2t threshold for the v cco bank 2 supply 0.4 1.0 v notes: 1. v ccint , v ccaux , and v cco supplies to the fpga can be applied in any order. however, the fpga?s configuration source (platform flash, spi flash, parallel nor flash, microcontroller) might have specific requirements. check the data sheet for the attached configu ration source. in step 0 devices using the hswap internal pull-up, v ccint must be applied before v ccaux . 2. to ensure successful power-on, v ccint , v cco bank 2, and v ccaux supplies must rise through their respective threshold-voltage ranges with no dips at any point. ta bl e 7 5 : supply voltage ramp rate symbol description min max units v ccintr ramp rate from gnd to valid v ccint supply level 0.2 50 ms v ccauxr ramp rate from gnd to valid v ccaux supply level 0.2 50 ms v cco2r ramp rate from gnd to valid v cco bank 2 supply level 0.2 50 ms notes: 1. v ccint , v ccaux , and v cco supplies to the fpga can be applied in any order. however, the fpga?s configuration source (platform flash, spi flash, parallel nor flash, microcontroller) might have specific requirements. check the data sheet for the attached configu ration source. in step 0 devices using the hswap internal pull-up, v ccint must be applied before v ccaux . 2. to ensure successful power-on, v ccint , v cco bank 2, and v ccaux supplies must rise through their respective threshold-voltage ranges with no dips at any point. ta bl e 7 6 : supply voltage levels necessary for preserving ram contents symbol description min units v drint v ccint level required to retain ram data 1.0 v v draux v ccaux level required to retain ram data 2.0 v notes: 1. ram contents include configuration data. dc and switching characteristics DS312-3 (v3.8) august 26, 2009 www.xilinx.com 119 product specification r general recommended o perating conditions ta bl e 7 7 : general recommended operating conditions symbol description min nominal max units t j junction temperature commercial 0 ? 85 c industrial ?40 ? 100 c v ccint internal supply voltage 1.140 1.200 1.260 v v cco (1) output driver supply voltage 1.100 - 3.465 v v ccaux auxiliary supply voltage 2.375 2.500 2.625 v v in (2,3,4,5) input voltage extremes to avoid turning on i/o protection diodes i/o, input-only, and dual-purpose pins (2) ?0.5 ? v cco + 0.5 v dedicated pins (3) ?0.5 ? v ccaux + 0.5 v t in input signal transition time (6) ?? 500 ns notes: 1. this v cco range spans the lowest and highest operating voltages for all supported i/o standards. ta b l e 8 0 lists the recommended v cco range specific to each of the single-ended i/o standards, and ta b l e 8 2 lists that specific to the differential standards. 2. each of the user i/o and dual-purpose pins is associated with one of the four banks? v cco rails. meeting the v in limit ensures that the internal diode junctions that exist between these pins and their associated v cco and gnd rails do not turn on. the absolute maximum rating is provided in ta b l e 7 3 . 3. all dedicated pins (prog_b, done, tck, tdi, tdo, and tms) draw power from the v ccaux rail (2.5v). meeting the v in max limit ensures that the internal diode junctions that exist between each of these pins and the v ccaux and gnd rails do not turn on. 4. input voltages outside the recommended range is permissible provided that the i ik input clamp diode rating is met and no more than 100 pins exceed the range simultaneously. refer to ta bl e 7 3 . 5. see xapp459 , "eliminating i/o coupling effects when interfacing large-swing single-ended signals to user i/o pins." 6. measured between 10% and 90% v cco . follow signal integrity recommendations. dc and switching characteristics 120 www.xilinx.com DS312-3 (v3.8) august 26, 2009 product specification r general dc characteristics for i/o pins ta bl e 7 8 : general dc characteristics of user i/o, dual-purpose, and dedicated pins symbol description test c onditions min typ max units i l leakage current at user i/o, input-only, dual-purpose, and dedicated pins driver is in a high-impedance state, v in = 0v or v cco max, sample-tested ?10 ? +10 a i rpu (2) current through pull-up resistor at user i/o, dual-purpose, input-only, and dedicated pins v in = 0v, v cco = 3.3v ?0.36 ? ?1.24 ma v in = 0v, v cco = 2.5v ?0.22 ? ?0.80 ma v in = 0v, v cco = 1.8v ?0.10 ? ?0.42 ma v in = 0v, v cco = 1.5v ?0.06 ? ?0.27 ma v in = 0v, v cco = 1.2v ?0.04 ? ?0.22 ma r pu (2) equivalent pull-up resistor value at user i/o, dual-purpose, input-only, and dedicated pins (based on i rpu per note 2) v in = 0v, v cco = 3.0v to 3.465v 2.4 ? 10.8 k v in = 0v, v cco = 2.3v to 2.7v 2.7 ? 11.8 k v in = 0v, v cco = 1.7v to 1.9v 4.3 ? 20.2 k v in = 0v, v cco =1.4v to 1.6v 5.0 ? 25.9 k v in = 0v, v cco = 1.14v to 1.26v 5.5 ? 32.0 k i rpd (2) current through pull-down resistor at user i/o, dual-purpose, input-only, and dedicated pins v in = v cco 0.10 ? 0.75 ma r pd (2) equivalent pull-down resistor value at user i/o, dual-purpose, input-only, and dedicated pins (based on i rpd per note 2) v in = v cco = 3.0v to 3.465v 4.0 ? 34.5 k v in = v cco = 2.3v to 2.7v 3.0 ? 27.0 k v in = v cco = 1.7v to 1.9v 2.3 ? 19.0 k v in = v cco = 1.4v to 1.6v 1.8 ? 16.0 k v in = v cco = 1.14v to 1.26v 1.5 ? 12.6 k i ref v ref current per pin all v cco levels ?10 ? +10 a c in input capacitance - ? ? 10 pf r dt resistance of optional differential termination circuit within a differential i/o pair. not available on input-only pairs. v ocm min v icm v ocm max v od min v id v od max v cco = 2.5v ?120? notes: 1. the numbers in this table are based on the conditions set forth in ta b l e 7 7 . 2. this parameter is based on characterization. the pull-up resistance r pu = v cco / i rpu . the pull-down resistance r pd =v in /i rpd . dc and switching characteristics DS312-3 (v3.8) august 26, 2009 www.xilinx.com 121 product specification r quiescent current requirements ta bl e 7 9 : quiescent supply current characteristics symbol description device typical (2) commercial maximum (2) industrial maximum (2) units i ccintq quiescent v ccint supply current xc3s100e 8 27 36 ma xc3s250e 15 78 104 ma xc3s500e 25 106 145 ma xc3s1200e 50 259 324 ma xc3s1600e 65 366 457 ma i ccoq quiescent v cco supply current xc3s100e 0.8 1.0 1.5 ma xc3s250e 0.8 1.0 1.5 ma xc3s500e 0.8 1.0 1.5 ma xc3s1200e 1.5 2.0 2.5 ma xc3s1600e 1.5 2.0 2.5 ma i ccauxq quiescent v ccaux supply current xc3s100e 8 12 13 ma xc3s250e 12 22 26 ma xc3s500e 18 31 34 ma xc3s1200e 35 52 59 ma xc3s1600e 45 76 86 ma notes: 1. the numbers in this table are based on the conditions set forth in ta b l e 7 7 . 2. quiescent supply current is measured with all i/o drivers in a high-impedance state and with all pull-up/pull-down resistors at the i/o pads disabled. typical values are characterized using typical devices at room temperature (t j of 25c at v ccint = 1.2 v, v cco = 3.3v, and v ccaux = 2.5v). the maximum limits are tested for each device at the respective maximum specified junction temperature and at maximum voltage limits with v ccint = 1.26v, v cco = 3.465v, and v ccaux = 2.625v. the fpga is programmed with a ?blank? configuration data file (i.e., a design with no functional elements instantiated). for conditions other than those described above, (e.g., a design including fu nctional elements), measured quiescent current levels may be different than the values in the table. for more accurate estimates for a s pecific design, use the xilinx? xpower tools. 3. there are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) the spartan-3e xpower estimator provides quick, approximate, typical estimates, and does not require a netlist of the design. b) xpower analyzer uses a netlist as input to provide maximum estimates as well as more accurate typical estimates. 4. the maximum numbers in this table indicate the minimum current ea ch power rail requires in order for the fpga to power-on suc cessfully. dc and switching characteristics 122 www.xilinx.com DS312-3 (v3.8) august 26, 2009 product specification r single-ended i/o standards ta bl e 8 0 : recommended operating conditions for user i/os using single-ended standards iostandard attribute v cco for drivers (2) v ref v il v ih min (v) nom (v) max (v) min (v) nom (v) max (v) max (v) min (v) lvttl 3.0 3.3 3.465 v ref is not used for these i/o standards 0.8 2.0 lv c m o s 3 3 (4) 3.0 3.3 3.465 0.8 2.0 lv c m o s 2 5 (4,5) 2.3 2.5 2.7 0.7 1.7 lvcmos18 1.65 1.8 1.95 0.4 0.8 lvcmos15 1.4 1.5 1.6 0.4 0.8 lvcmos12 1.1 1.2 1.3 0.4 0.7 pci33_3 (6) 3.0 3.3 3.465 0.3 ? v cco 0.5 ? v cco pci66_3 (6) 3.0 3.3 3.465 0.3 ? v cco 0.5 ? v cco hstl_i_18 1.7 1.8 1.9 0.8 0.9 1.1 v ref - 0.1 v ref + 0.1 hstl_iii_18 1.7 1.8 1.9 - 1.1 - v ref - 0.1 v ref + 0.1 sstl18_i 1.7 1.8 1.9 0.833 0.900 0.969 v ref - 0.125 v ref + 0.125 sstl2_i 2.3 2.5 2.7 1.15 1.25 1.35 v ref - 0.125 v ref + 0.125 notes: 1. descriptions of the symbols used in this table are as follows: v cco ? the supply voltage for output drivers v ref ? the reference voltage for setting the input switching threshold v il ? the input voltage that indicates a low logic level v ih ? the input voltage that indicates a high logic level 2. the v cco rails supply only output drivers, not input circuits. 3. for device operation, the maximum signal voltage (v ih max) may be as high as v in max. see ta bl e 7 3 . 4. there is approximately 100 mv of hysteresis on inputs using lvcmos33 and lvcmos25 i/o standards. 5. all dedicated pins (prog_b, done, tck, tdi, tdo, and tm s) use the lvcmos25 standard and draw power from the v ccaux rail (2.5v). the dual-purpose configuration pins use the lvcmos standard before the user mode. when using these pins as part of a standard 2 .5v configuration interface, apply 2.5v to the v cco lines of banks 0, 1, and 2 at power-on as well as throughout configuration. 6. for information on pci ip solutions, see www.xilinx.com/pci. the pcix iostandard is available and has equivalent characteristics but no pci-x ip is supported. dc and switching characteristics DS312-3 (v3.8) august 26, 2009 www.xilinx.com 123 product specification r ta bl e 8 1 : dc characteristics of user i/os using single-ended standards iostandard attribute test conditions logic level characteristics i ol (ma) i oh (ma) v ol max (v) v oh min (v) lv t t l (3) 2 2 ?2 0.4 2.4 44?4 66?6 88?8 12 12 ?12 16 16 ?16 lv c m o s 3 3 (3) 2 2 ?2 0.4 v cco ? 0.4 44?4 66?6 88?8 12 12 ?12 16 16 ?16 lv c m o s 2 5 (3) 2 2 ?2 0.4 v cco ? 0.4 44?4 66?6 88?8 12 12 ?12 lv c m o s 1 8 (3) 22?2 0.4 v cco ? 0.4 44?4 66?6 88?8 lv c m o s 1 5 (3) 22?2 0.4 v cco ? 0.4 44?4 66?6 lv c m o s 1 2 (3) 22?2 0.4 v cco - 0.4 pci33_3 (4) 1.5 ?0.5 10% v cco 90% v cco pci66_3 (4) 1.5 ?0.5 10% v cco 90% v cco hstl_i_18 8 ?8 0.4 v cco - 0.4 hstl_iii_18 24 ?8 0.4 v cco - 0.4 sstl18_i 6.7 ?6.7 v tt ? 0.475 v tt + 0.475 sstl2_i 8.1 ?8.1 v tt ? 0.61 v tt + 0.61 notes: 1. the numbers in this table are based on the conditions set forth in ta b l e 7 7 and ta bl e 8 0 . 2. descriptions of the symbols used in this table are as follows: i ol ? the output current condition under which v ol is tested i oh ? the output current condition under which v oh is tested v ol ? the output voltage that indicates a low logic level v oh ? the output voltage that indicates a high logic level v cco ? the supply voltage for output drivers v tt ? the voltage applied to a resistor termination 3. for the lvcmos and lvttl standards: the same v ol and v oh limits apply for both the fast and slow slew attributes. 4. tested according to the relevant pci specifications. for information on pci ip solutions, see www.xilinx.com/pci . the pcix iostandard is available and has equivalent characteristics but no pci-x ip is supported. table 81: dc characteristics of user i/os using single-ended standards (continued) iostandard attribute test conditions logic level characteristics i ol (ma) i oh (ma) v ol max (v) v oh min (v) dc and switching characteristics 124 www.xilinx.com DS312-3 (v3.8) august 26, 2009 product specification r differential i/o standards figure 70: differential input voltages ta bl e 8 2 : recommended operating conditions for user i/ os using differential signal standards iostandard attribute v cco for drivers (1) v id v icm min (v) nom (v) max (v) min (mv) nom (mv) max (mv) min (v) nom (v) max (v) lvds_25 2.375 2.50 2.625 100 350 600 0.30 1.25 2.20 blvds_25 2.375 2.50 2.625 100 350 600 0.30 1.25 2.20 mini_lvds_25 2.375 2.50 2.625 200 - 600 0.30 - 2.2 lvpecl_25 (2) inputs only 100 800 1000 0.5 1.2 2.0 rsds_25 2.375 2.50 2.625 100 200 - 0.3 1.20 1.4 diff_hstl_i_18 1.7 1. 8 1.9 100 - - 0.8 - 1.1 diff_hstl_iii_18 1.7 1.8 1.9 100 - - 0.8 - 1.1 diff_sstl18_i 1.7 1.8 1.9 100 - - 0.7 - 1.1 diff_sstl2_i 2.3 2.5 2.7 100 - - 1.0 - 1.5 notes: 1. the v cco rails supply only differential output drivers, not input circuits. 2. v ref inputs are not used for any of the differential i/o standards. ds099-3_01_012304 v inn v inp gnd le v el 50% v icm v icm = inp u t common mode v oltage = v id v inp internal logic differential i/o pair pins v inn n p 2 v inp + v inn v id = differential inp u t v oltage = v inp - v inn dc and switching characteristics DS312-3 (v3.8) august 26, 2009 www.xilinx.com 125 product specification r figure 71: differential output voltages ta bl e 8 3 : dc characteristics of user i/os using differential signal standards iostandard attribute v od v od v ocm v ocm v oh v ol min (mv) typ (mv) max (mv) min (mv) max (mv) min (v) typ (v) max (v) min (mv) max (mv) min (v) max (v) lvds_25 250 350 450 ? ?1.125 ?1.375 ? ? ? ? blvds_25 250 350 450 ? ? ?1.20 ? ? ? ? ? mini_lvds_25 300 ? 600 ?501.0 ?1.4 ?50 ? ? rsds_25 100 ? 400 ? ?1.1 ?1.4 ?? ? ? diff_hstl_i_18 ? ? ? ? ? ? ? ? ? ?v cco ? 0.4 0.4 diff_hstl_iii_18 ? ? ? ? ? ? ? ? ? ?v cco ? 0.4 0.4 diff_sstl18_i ? ? ? ? ? ? ? ? ? ? v tt + 0.475 v tt ? 0.475 diff_sstl2_i ? ? ? ? ? ? ? ? ? ?v tt + 0.61 v tt ? 0.61 notes: 1. the numbers in this table are based on the conditions set forth in ta b l e 7 7 and ta bl e 8 2 . 2. output voltage measurements for all differential standards are made with a termination resistor (r t ) of 100 across the n and p pins of the differential signal pair. the exception is for blvds, shown in figure 72 below. 3. at any given time, no more than two of the following differential output standards may be assigned to an i/o bank: lvds_25, r sds_25, mini_lvds_25 figure 72: external termination resistors for blvds transmitter and blvds receiver DS312-3_03_021505 v outn v outp gnd le v el 50% v ocm v ocm v od v ol v oh v outp internal logic v outn n p = o u tp u t common mode v oltage = 2 v outp + v outn v od = o u tp u t differential v oltage = v oh = o u tp u t v oltage indicating a high logic le v el v ol = o u tp u t v oltage indicating a low logic le v el v outp - v outn differential i/o pair pins z 0 = 50 z 0 = 50 140 165 165 100 DS312-3_07_04110 8 v cco = 2.5 v 1/4th of bo u rns part nu m b er cat16-l v 4f12 v cco = 2.5 v 1/4th of bo u rns part nu m b er cat16-pt4f4 fpga in fpga o u t dc and switching characteristics 126 www.xilinx.com DS312-3 (v3.8) august 26, 2009 product specification r switching characteristics all spartan-3e fpgas ship in two speed grades: ?4 and the higher performance ?5. switching characteristics in this document may be designated as advance, preliminary, or production, as shown in ta bl e 8 4 . each category is defined as follows: advance : these specifications are based on simulations only and are typically available soon after establishing fpga specifications. although speed grades with this des- ignation are considered relatively stable and conservative, some under-reporting might still occur. preliminary : these specifications are based on complete early silicon characterizati on. devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. the probability of under-reporting pr eliminary delays is greatly reduced compared to advance data. production : these specifications are approved once enough production s ilicon of a particular device family mem- ber has been characterized to provide full correlation between speed files and devices over numerous production lots. there is no under-reporting of delays, and customers receive formal notification of any subsequent changes. typ- ically, the slowest speed grades transition to production before faster speed grades. software version requirements production-quality systems must use fpga designs com- piled using a speed file designated as production sta- tus. fpgas designs using a less mature speed file designation should only be used during system prototyping or pre-production qualification. fpga designs with speed files designated as advance or preliminary should not be used in a production-quality system. whenever a speed file designation changes, as a device matures toward production st atus, rerun the latest xilinx ise software on the fpga design to ensure that the fpga design incorporates the latest timing information and soft- ware updates. all parameter limits are representative of worst-case supply voltage and junction temperature conditions. unless other- wise noted, the published parameter values apply to all spartan-3e devices. ac and dc characteristics are specified using the same numbers for both commercial and industrial grades. to create a xilinx mysupport user account and sign up for automatic e-mail notification whenever this data sheet is updated: ? sign up for alerts on xilinx mysupport http://www.xilinx.com/support/answers/19380.htm timing parameters and their representative values are selected for inclusion below either because they are impor- tant as general design requirements or they indicate funda- mental device performance characteristics. the spartan-3e speed files (v1.27), part of the xilinx development software, are the original source for many but not all of the values. the speed grade designations for these files are shown in ta b l e 8 4 . for more complete, more precise, and worst-case data, use the values reported by the xilinx static timing ana- lyzer (trace in the xilinx development software) and back-annotated to the simulation netlist. ta b l e 8 5 provides the history of the spartan-3e speed files since all devices reached production status. table 84: spartan-3e v1.27 speed grade designations device advance preliminary production xc3s100e ? min, ? 4, ? 5 xc3s250e ? min, ? 4, ? 5 xc3s500e ? min, ? 4, ? 5 xc3s1200e ? min, ? 4, ? 5 xc3s1600e ? min, ? 4, ? 5 table 85: spartan-3e speed file version history version ise release description 1.27 9.2.03i added xa automotive. 1.26 8.2.02i added -0/-min speed grade, which includes minimum values. 1.25 8.2.01i added xa automotive devices to speed file. improved model for left and right dcms. 1.23 8.2i updated input setup/hold values based on default ifd_delay_value settings. 1.21 8.1.03i all spartan-3e fpgas and all speed grades elevated to production status. dc and switching characteristics DS312-3 (v3.8) august 26, 2009 www.xilinx.com 127 product specification r i/o timing ta bl e 8 6 : pin-to-pin clock-to-output times for the iob output path symbol description conditions device speed grade units -5 -4 max max clock-to-output times t ickofdcm when reading from the output flip-flop (off), the time from the active transition on the global clock pin to data appearing at the output pin. the dcm is used. lv c m o s 2 5 (2) , 12 ma output drive, fast slew rate, with dcm (3) xc3s100e 2.66 2.79 ns xc3s250e 3.00 3.45 ns xc3s500e 3.01 3.46 ns xc3s1200e 3.01 3.46 ns xc3s1600e 3.00 3.45 ns t ickof when reading from off, the time from the active transition on the global clock pin to data appearing at the output pin. the dcm is not used. lv c m o s 2 5 (2) , 12 ma output drive, fast slew rate, without dcm xc3s100e 5.60 5.92 ns xc3s250e 4.91 5.43 ns xc3s500e 4.98 5.51 ns xc3s1200e 5.36 5.94 ns xc3s1600e 5.45 6.05 ns notes: 1. the numbers in this table are tested using the methodology presented in ta bl e 9 5 and are based on the operating conditions set forth in ta bl e 7 7 and ta b l e 8 0 . 2. this clock-to-output time requires adjustment whenever a si gnal standard other than lvcmos25 is assigned to the global clock input or a standard other than lvcmos25 with 12 ma drive and fast slew ra te is assigned to the data output. if the former is true, add the appropriate input adjustment from ta bl e 9 1 . if the latter is true, add the appropriate output adjustment from ta bl e 9 4 . 3. dcm output jitter is included in all measurements. 4. for minimums, use the values reported by the xilinx timing analyzer. dc and switching characteristics 128 www.xilinx.com DS312-3 (v3.8) august 26, 2009 product specification r ta bl e 8 7 : pin-to-pin setup and hold times for the iob input path (system synchronous) symbol description conditions ifd_ delay_ value= device speed grade units -5 -4 min min setup times t psdcm when writing to the input flip-flop (iff), th e time from the setup of data at the input pin to the active transition at a global clock pin. the dcm is used. no input delay is programmed. lv c m o s 2 5 (2) , ifd_delay_value = 0, with dcm (4) 0 xc3s100e 2.65 2.98 ns xc3s250e 2.25 2.59 ns xc3s500e 2.25 2.59 ns xc3s1200e 2.25 2.58 ns xc3s1600e 2.25 2.59 ns t psfd when writing to iff, the time from the setup of data at the input pin to an active transition at the global clock pin. the dcm is not used. the input delay is programmed. lv c m o s 2 5 (2) , ifd_delay_value = default software setting 2 xc3s100e 3.16 3.58 ns 3 xc3s250e 3.44 3.91 ns 3 xc3s500e 4.00 4.73 ns 3 xc3s1200e 2.60 3.31 ns 3 xc3s1600e 3.33 3.77 ns hold times t phdcm when writing to iff, the time from the active transition at the global clock pin to the point when data must be held at the input pin. the dcm is used. no input delay is programmed. lv c m o s 2 5 (3) , ifd_delay_value = 0, with dcm (4) 0 xc3s100e ?0.54 ?0.52 ns xc3s250e 0.06 0.14 ns xc3s500e 0.07 0.14 ns xc3s1200e 0.07 0.15 ns xc3s1600e 0.06 0.14 ns t phfd when writing to iff, the time from the active transition at the global clock pin to the point when data must be held at the input pin. the dcm is not used. the input delay is programmed. lv c m o s 2 5 (3) , ifd_delay_value = default software setting 2 xc3s100e ?0.31 ?0.24 ns 3 xc3s250e ?0.32 ?0.32 ns 3 xc3s500e ?0.77 ?0.77 ns 3 xc3s1200e 0.13 0.16 ns 3 xc3s1600e ?0.05 ?0.03 ns notes: 1. the numbers in this table are tested using the methodology presented in ta bl e 9 5 and are based on the operating conditions set forth in ta bl e 7 7 and ta b l e 8 0 . 2. this setup time requires adjustment whenever a signal standard other than lvcmos25 is assigned to the global clock input or t he data input. if this is true of the global clock input, subtract the appropriate adjustment from ta bl e 9 1 . if this is true of the data input, add the appropriate input adjustment from the same table. 3. this hold time requires adjustment whenever a signal standard other than lvcmos25 is assigned to the global clock input or th e data input. if this is true of the global clock input, add the appropriate input adjustment from ta bl e 9 1 . if this is true of the data input, subtract the appropriate input adjustment from the same table. when the hold time is negative, it is possible to change the data before the clock?s active edge. 4. dcm output jitter is included in all measurements. dc and switching characteristics DS312-3 (v3.8) august 26, 2009 www.xilinx.com 129 product specification r ta bl e 8 8 : setup and hold times for the iob input path symbol description conditions ifd_ delay_ value= device speed grade units -5 -4 min min setup times t iopick time from the setup of data at the input pin to the active transition at the iclk input of the input flip-flop (iff). no input delay is programmed. lv c m o s 2 5 (2) , ifd_delay_value = 0 0all 1.84 2.12 ns t iopickd time from the setup of data at the input pin to the active transition at the iff?s iclk input. the input delay is programmed. lv c m o s 2 5 (2) , ifd_delay_value = default software setting 2xc3s100e 6.12 7.01 ns 3 all others 6.76 7.72 hold times t ioickp time from the active transition at the iff?s iclk input to the point where data must be held at the input pin. no input delay is programmed. lv c m o s 2 5 (2) , ifd_delay_value = 0 0all ?0.76 ?0.76 ns t ioickpd time from the active transition at the iff?s iclk input to the point where data must be held at the input pin. the input delay is programmed. lv c m o s 2 5 (2) , ifd_delay_value = default software setting 2xc3s100e ?3.93 ?3.93 ns 3 all others ?3.50 ?3.50 set/reset pulse width t rpw_iob minimum pulse width to sr control input on iob all 1.57 1.80 ns notes: 1. the numbers in this table are tested using the methodology presented in ta bl e 9 5 and are based on the operating conditions set forth in ta bl e 7 7 and ta b l e 8 0 . 2. this setup time requires adjustment whenever a signal standard other than lvcmos25 is assigned to the data input. if this is true, add the appropriate input adjustment from ta bl e 9 1 . 3. these hold times require adjustment whenever a signal standard other than lvcmos25 is assigned to the data input. if this is true, subtract the appropriate input adjustment from ta b l e 9 1 . when the hold time is negative, it is possible to change the data before the clock?s active edge. ta bl e 8 9 : sample window (source synchronous) symbol description max units t samp setup and hold capture window of an iob input flip-flop the input capture sample window va lue is highly specific to a particular application, device, package, i/o standard, i/o placement, dcm usage, and clock buffer. please consult the appropriate xilinx application note for application-specific values. ? xapp485 : 1:7 deserialization in spartan-3e fpgas at speeds up to 666 mbps ps dc and switching characteristics 130 www.xilinx.com DS312-3 (v3.8) august 26, 2009 product specification r ta bl e 9 0 : propagation times for the iob input path symbol description conditions ifd_ delay_ value= device speed grade units -5 -4 max max propagation times t iopli the time it takes for data to travel from the input pin through the iff latch to the i output with no input delay programmed lv c m o s 2 5 (2) , ifd_delay_value = 0 0 all 1.96 2.25 ns t ioplid the time it takes for data to travel from the input pin through the iff latch to the i output with the input delay programmed lv c m o s 2 5 (2) , ifd_delay_value = default software setting 2 xc3s100e 5.40 5.97 ns 3 all others 6.30 7.20 notes: 1. the numbers in this table are tested using the methodology presented in ta bl e 9 5 and are based on the operating conditions set forth in ta bl e 7 7 and ta b l e 8 0 . 2. this propagation time requires adjustment whenever a signal standard other than lvcmos25 is assigned to the data input. when this is true, add the appropriate input adjustment from ta bl e 9 1 . table 91: input timing adjustments by iostandard convert input time from lvcmos25 to the following signal standard (iostandard) add the adjustment below units speed grade -5 -4 single-ended standards lv t t l 0 . 4 2 0 . 4 3 n s lvcmos33 0.42 0.43 ns lv c m o s 2 5 0 0 n s lvcmos18 0.96 0.98 ns lvcmos15 0.62 0.63 ns lvcmos12 0.26 0.27 ns pci33_3 0.41 0.42 ns pci66_3 0.41 0.42 ns hstl_i_18 0.12 0.12 ns hstl_iii_18 0.17 0.17 ns sstl18_i 0.30 0.30 ns sstl2_i 0.15 0.15 ns differential standards lvds_25 0.48 0.49 ns blvds_25 0.39 0.39 ns mini_lvds_25 0.48 0.49 ns lvpecl_25 0.27 0.27 ns rsds_25 0.48 0.49 ns diff_hstl_i_18 0.48 0.49 ns diff_hstl_iii_18 0.48 0.49 ns diff_sstl18_i 0.30 0.30 ns diff_sstl2_i 0.32 0.32 ns notes: 1. the numbers in this table are tested using the methodology presented in ta bl e 9 5 and are based on the operating conditions set forth in ta bl e 7 7 , ta bl e 8 0 , and ta bl e 8 2 . 2. these adjustments are used to convert input path times originally specified for the lvcmos25 standard to times that correspond to other signal standards. table 91: input timing adjustments by iostandard convert input time from lvcmos25 to the following signal standard (iostandard) add the adjustment below units speed grade -5 -4 dc and switching characteristics DS312-3 (v3.8) august 26, 2009 www.xilinx.com 131 product specification r ta bl e 9 2 : timing for the iob output path symbol description conditions device speed grade units -5 -4 max max clock-to-output times t iockp when reading from the output flip-flop (off), the time from the active transition at the oclk input to data appearing at the output pin lv c m o s 2 5 (2) , 12 ma output drive, fast slew rate all 2.18 2.50 ns propagation times t ioop the time it takes for data to travel from the iob?s o input to the output pin lv c m o s 2 5 (2) , 12 ma output drive, fast slew rate all 2.24 2.58 ns t ioolp the time it takes for data to travel from the o input through the off latch to the output pin 2.32 2.67 ns set/reset times t iosrp time from asserting the off?s sr input to setting/resetting data at the output pin lv c m o s 2 5 (2) , 12 ma output drive, fast slew rate all 3.27 3.76 ns t iogsrq time from asserting the global set reset (gsr) input on the startup_spartan3e primitive to setting/resetting data at the output pin 8.40 9.65 ns notes: 1. the numbers in this table are tested using the methodology presented in ta bl e 9 5 and are based on the operating conditions set forth in ta bl e 7 7 and ta b l e 8 0 . 2. this time requires adjustment whenever a signal standard other th an lvcmos25 with 12 ma drive and fast slew rate is assigned to the data output. when this is true, add the appropriate output adjustment from ta bl e 9 4 . 3. for minimum delays use the values reported by the timing analyzer. dc and switching characteristics 132 www.xilinx.com DS312-3 (v3.8) august 26, 2009 product specification r ta bl e 9 3 : timing for the iob three-state path symbol description conditions device speed grade units -5 -4 max max synchronous output enable/disable times t iockhz time from the active transition at the otclk input of the three-state flip-flop (tff) to when the output pin enters the high-impedance state lv c m o s 2 5 , 12 ma output drive, fast slew rate all 1.49 1.71 ns t iockon (2) time from the active transition at tff?s otclk input to when the output pin drives valid data all 2.70 3.10 ns asynchronous output enable/disable times t gts time from asserting the global three state (gts) input on the startup_spartan3e primitive to when the output pin enters the high-impedance state lv c m o s 2 5 , 12 ma output drive, fast slew rate all 8.52 9.79 ns set/reset times t iosrhz time from asserting tff?s sr input to when the output pin enters a high-impedance state lv c m o s 2 5 , 12 ma output drive, fast slew rate all 2.11 2.43 ns t iosron (2) time from asserting tff?s sr input at tff to when the output pin drives valid data all 3.32 3.82 ns notes: 1. the numbers in this table are tested using the methodology presented in ta bl e 9 5 and are based on the operating conditions set forth in ta bl e 7 7 and ta b l e 8 0 . 2. this time requires adjustment whenever a signal standard other t han lvcmos25 with 12 ma drive and fast slew rate is assigned to the data output. when this is true, add the appropriate output adjustment from ta bl e 9 4 . 3. for minimum delays use the values reported by the timing analyzer. dc and switching characteristics DS312-3 (v3.8) august 26, 2009 www.xilinx.com 133 product specification r ta bl e 9 4 : output timing adjustments for iob convert output time from lvcmos25 with 12ma drive and fast slew rate to the following signal standard (iostandard) add the adjustment below units speed grade -5 -4 single-ended standards lvttl slow 2 ma 5.20 5.41 ns 4 ma 2.32 2.41 ns 6 ma 1.83 1.90 ns 8 ma 0.64 0.67 ns 12 ma 0.68 0.70 ns 16 ma 0.41 0.43 ns fast 2 ma 4.80 5.00 ns 4 ma 1.88 1.96 ns 6 ma 1.39 1.45 ns 8 ma 0.32 0.34 ns 12 ma 0.28 0.30 ns 16 ma 0.28 0.30 ns lvcmos33 slow 2 ma 5.08 5.29 ns 4 ma 1.82 1.89 ns 6 ma 1.00 1.04 ns 8 ma 0.66 0.69 ns 12 ma 0.40 0.42 ns 16 ma 0.41 0.43 ns fast 2 ma 4.68 4.87 ns 4 ma 1.46 1.52 ns 6 ma 0.38 0.39 ns 8 ma 0.33 0.34 ns 12 ma 0.28 0.30 ns 16 ma 0.28 0.30 ns lvcmos25 slow 2 ma 4.04 4.21 ns 4 ma 2.17 2.26 ns 6 ma 1.46 1.52 ns 8 ma 1.04 1.08 ns 12 ma 0.65 0.68 ns fast 2 ma 3.53 3.67 ns 4 ma 1.65 1.72 ns 6 ma 0.44 0.46 ns 8 ma 0.20 0.21 ns 12 ma 0 0 ns lvcmos18 slow 2 ma 5.03 5.24 ns 4 ma 3.08 3.21 ns 6 ma 2.39 2.49 ns 8 ma 1.83 1.90 ns fast 2 ma 3.98 4.15 ns 4 ma 2.04 2.13 ns 6 ma 1.09 1.14 ns 8 ma 0.72 0.75 ns lvcmos15 slow 2 ma 4.49 4.68 ns 4 ma 3.81 3.97 ns 6 ma 2.99 3.11 ns fast 2 ma 3.25 3.38 ns 4 ma 2.59 2.70 ns 6 ma 1.47 1.53 ns lvcmos12 slow 2 ma 6.36 6.63 ns fast 2 ma 4.26 4.44 ns hstl_i_18 0.33 0.34 ns hstl_iii_18 0.53 0.55 ns pci33_3 0.44 0.46 ns pci66_3 0.44 0.46 ns sstl18_i 0.24 0.25 ns sstl2_i ?0.20 ?0.20 ns differential standards lvds_25 ?0.55 ?0.55 ns blvds_25 0.04 0.04 ns mini_lvds_25 ?0.56 ?0.56 ns lvpecl_25 input only ns rsds_25 ?0.48 ?0.48 ns diff_hstl_i_18 0.42 0.42 ns diff_hstl_iii_18 0.53 0.55 ns diff_sstl18_i 0.40 0.40 ns diff_sstl2_i 0.44 0.44 ns notes: 1. the numbers in this table are tested using the methodology presented in ta bl e 9 5 and are based on the operating conditions set forth in ta b l e 7 7 , ta b l e 8 0 , and ta bl e 8 2 . 2. these adjustments are used to convert output- and three-state-path times originally specified for the lvcmos25 standard with 12 ma drive and fast slew rate to times that correspond to other signal standards. do not adjust times that measure when outputs go into a high-impedance state. table 94: output timing adjustments for iob (continued) convert output time from lvcmos25 with 12ma drive and fast slew rate to the following signal standard (iostandard) add the adjustment below units speed grade -5 -4 dc and switching characteristics 134 www.xilinx.com DS312-3 (v3.8) august 26, 2009 product specification r timing measurement methodology when measuring timing parameters at the programmable i/os, different signal standards call for different test condi- tions. ta bl e 9 5 lists the conditions to use for each standard. the method for measuring input timing is as follows: a sig- nal that swings between a low logic level of v l and a high logic level of v h is applied to the input under test. some standards also require the application of a bias voltage to the v ref pins of a given bank to properly set the input-switching threshold. the measurement point of the input signal (v m ) is commonly located halfway between v l and v h . the output test setup is shown in figure 73 . a termination voltage v t is applied to the termination resistor r t , the other end of which is connected to the output. for each standard, r t and v t generally take on the standard values recom- mended for minimizing signal reflections. if the standard does not ordinarily use terminations (e.g., lvcmos, lvttl), then r t is set to 1m to indicate an open connec- tion, and v t is set to zero. the same measurement point (v m ) that was used at the input is also used at the output. figure 73: output test setup fpga output v t (v ref ) r t (r ref ) v m (v meas ) c l (c ref ) DS312-3_04_090105 notes: 1. the names shown in parentheses are used in the ibis file. ta bl e 9 5 : test methods for timing measurement at i/os signal standard (iostandard) inputs outputs inputs and outputs v ref (v) v l (v) v h (v) r t ( )v t (v) v m (v) single-ended lvttl -03.31m01.4 lvcmos33 - 0 3.3 1m 0 1.65 lvcmos25 - 0 2.5 1m 0 1.25 lvcmos18 - 0 1.8 1m 0 0.9 lvcmos15 - 0 1.5 1m 0 0.75 lvcmos12 - 0 1.2 1m 0 0.6 pci33_3 rising - note 3 note 3 25 0 0.94 falling 25 3.3 2.03 pci66_3 rising - note 3 note 3 25 0 0.94 falling 25 3.3 2.03 hstl_i_18 0.9 v ref ? 0.5 v ref + 0.5 50 0.9 v ref hstl_iii_18 1.1 v ref ? 0.5 v ref + 0.5 50 1.8 v ref sstl18_i 0.9 v ref ? 0.5 v ref + 0.5 50 0.9 v ref sstl2_i 1.25 v ref ? 0.75 v ref + 0.75 50 1.25 v ref differential lvds_25 - v icm ? 0.125 v icm + 0.125 50 1.2 v icm blvds_25 - v icm ? 0.125 v icm + 0.125 1m 0 v icm mini_lvds_25 - v icm ? 0.125 v icm + 0.125 50 1.2 v icm lvpecl_25 - v icm ? 0.3 v icm + 0.3 1m 0 v icm rsds_25 - v icm ? 0.1 v icm + 0.1 50 1.2 v icm diff_hstl_i_18 - v ref ? 0.5 v ref + 0.5 50 0.9 v icm diff_hstl_iii_18 - v ref ? 0.5 v ref + 0.5 50 1.8 v icm dc and switching characteristics DS312-3 (v3.8) august 26, 2009 www.xilinx.com 135 product specification r the capacitive load (c l ) is connected between the output and gnd. the output timing for all standards, as published in the speed files and the data sheet, is always based on a c l value of zero. high-impedance probes (less than 1 pf) are used for all measurements. any delay that the test fix- ture might contribute to test measurements is subtracted from those measurements to produce the final timing num- bers as published in the speed files and data sheet. using ibis models to simulate load conditions in application ibis models permit the most accurate prediction of timing delays for a given application. the parameters found in the ibis model (v ref , r ref , and v meas ) correspond directly with the parameters used in ta b l e 9 5 (v t , r t , and v m ). do not confuse v ref (the termination voltage) from the ibis model with v ref (the input-switching threshold) from the table. a fourth parameter, c ref , is always zero. the four parameters describe all relevant output test conditions. ibis models are found in the xilinx development software as well as at the following link: http://www.xilinx.com/support/download/index.htm delays for a given application are simulated according to its specific load conditions as follows: 1. simulate the desired signal standard with the output driver connected to the test setup shown in figure 73 . use parameter values v t , r t , and v m from ta bl e 9 5 . c ref is zero. 2. record the time to v m . 3. simulate the same signal standard with the output driver connected to the pcb trace with load. use the appropriate ibis model (including v ref , r ref , c ref , and v meas values) or capacitive value to represent the load. 4. record the time to v meas . 5. compare the results of steps 2 and 4. add (or subtract) the increase (or decrease) in delay to (or from) the diff_sstl18_i - v ref ? 0.5 v ref + 0.5 50 0.9 v icm diff_sstl2_i - v ref ? 0.5 v ref + 0.5 50 1.25 v icm notes: 1. descriptions of the relevant symbols are as follows: v ref ? the reference voltage for setting the input switching threshold v icm ? the common mode input voltage v m ? voltage of measurement point on signal transition v l ? low-level test voltage at input pin v h ? high-level test voltage at input pin r t ? effective termination resistance, which takes on a value of 1m when no parallel termination is required v t ? termination voltage 2. the load capacitance (c l ) at the output pin is 0 pf for all signal standards. 3. according to the pci specification. ta bl e 9 5 : test methods for timing measurement at i/os (continued) signal standard (iostandard) inputs outputs inputs and outputs v ref (v) v l (v) v h (v) r t ( )v t (v) v m (v) dc and switching characteristics 136 www.xilinx.com DS312-3 (v3.8) august 26, 2009 product specification r simultaneously switchi ng output guidelines this section provides guidelines for the recommended max- imum allowable number of si multaneous switching outputs (ssos). these guidelines describe the maximum number of user i/o pins of a given output signal standard that should simultaneously switch in the sa me direction, while maintain- ing a safe level of switching noise. meeting these guidelines for the stated test conditions ensures that the fpga oper- ates free from the adverse effects of ground and power bounce. ground or power bounce occurs when a large number of outputs simultaneously switch in the same direction. the output drive transistors all conduct current to a common voltage rail. low-to-high transitions conduct to the v cco rail; high-to-low transitions conduct to the gnd rail. the resulting cumulative current transient induces a voltage dif- ference across the inductance that exists between the die pad and the power supply or ground return. the inductance is associated with bonding wires, the package lead frame, and any other signal routing inside the package. other vari- ables contribute to sso noise levels, including stray induc- tance on the pcb as well as capacitive loading at receivers. any sso-induced voltage consequently affects internal switching noise margins and ultimately signal quality. ta bl e 9 6 and ta b l e 9 7 provide the essential sso guide- lines. for each device/package combination, ta b l e 9 6 pro- vides the number of equivalent v cco /gnd pairs. the equivalent number of pairs is based on characterization and might not match the physical number of pairs. for each out- put signal standard and drive strength, ta bl e 9 7 recom- mends the maximum number of ssos, switching in the same direction, allowed per v cco /gnd pair within an i/o bank. the guidelines in ta bl e 9 7 are categorized by pack- age style. multiply the appropriate numbers from ta bl e 9 6 and ta bl e 9 7 to calculate the maximum number of ssos allowed within an i/o bank. exceeding these sso guide- lines might result in increased power or ground bounce, degraded signal integrity, or increased system jitter. sso max /io bank = ta b l e 9 6 x ta bl e 9 7 the recommended maximum sso values assumes that the fpga is soldered on the printed circuit board and that the board uses sound design practices. the sso values do not apply for fpgas mounted in sockets, due to the lead induc- tance introduced by the socket. the number of ssos allowed for quad-flat packages (vq, tq, pq) is lower than for ball grid array packages (fg) due to the larger lead inductance of the quad-flat packages. the results for chip-scale packaging (cp132) are better than quad-flat packaging but not as high as for ball grid array packaging. ball grid array packages are recommended for applications with a large number of simultaneously switch- ing outputs. ta bl e 9 6 : equivalent v cco /gnd pairs per bank device package style (including pb-free) vq100 cp132 tq144 pq208 ft256 fg320 fg400 fg484 xc3s100e 2 2 2 - - - - - xc3s250e 2 2 2 3 4 - - - xc3s500e 2 2 -345 - - xc3s1200e - - - - 4 5 6 - xc3s1600e - - - - -567 dc and switching characteristics DS312-3 (v3.8) august 26, 2009 www.xilinx.com 137 product specification r ta bl e 9 7 : recommended number of simultaneously switching outputs per v cco -gnd pair signal standard (iostandard) package type vq 100 tq 144 pq 208 cp 132 ft256, fg320, fg400, fg484 single-ended standards lvttl slow 2 34 20 19 52 60 417101026 41 6 17 10 7 26 29 8 8 6 6 13 22 12 8 6 5 13 13 165556 11 fast217171726 34 4 9 9 9 13 20 6 7 7 7 13 15 86 6 6 6 12 125556 10 165555 9 lvcmos33slow234202052 76 417101026 46 6 17 10 7 26 27 8 8 6 6 13 20 12 8 6 5 13 13 165556 10 fast217171726 44 4 8 8 8 13 26 6 8 6 6 13 16 86 6 6 6 12 125556 10 168855 8 lvcmos25slow228161642 76 413101019 46 6137 719 33 86 6 6 9 24 126669 18 fast217161626 42 4 9 9 9 13 20 6 9 7 7 13 15 86 6 6 6 13 125556 11 lvcmos18 slow 2 19 11 8 29 64 413 7 6 19 34 66559 22 86449 18 fast 2 13 8 8 19 36 4 8 5 5 13 21 64446 13 84446 10 lvcmos15slow216101019 55 48779 31 66559 18 fast 2 9 9 9 13 25 47777 16 65555 13 lvcmos12slow217111116 55 fast210101010 31 pci33_3 8 8 8 16 16 pci66_3 8 8 8 13 13 pcix 7 7 7 11 11 hstl_i_18 10 10 10 16 17 hstl_iii_18 10 10 10 16 16 sstl18_i 9 9 9 15 15 sstl2_i 12 12 12 18 18 differential standards (number of i/o pairs or channels) lvds_25 6 6 6 12 20 blvds_25 4 4 4 4 4 mini_lvds_25 6 6 6 12 20 lvpecl_25 input only rsds_25 6 6 6 12 20 diff_hstl_i_18 5 5 5 8 8 diff_hstl_iiii_18 5 5 5 8 8 diff_sstl18_i 4 4 4 7 7 diff_sstl2_i 6 6 6 9 8 notes: 1. the numbers in this table are recommendations that assume sound board layout practice. this table assumes the following parasitic factors: combined pcb trace and land inductance per v cco and gnd pin of 1.0 nh, receiver capacitive load of 15 pf. test limits are the vil/vih voltage limits for the respective i/o standard. 2. the pq208 results are based on physical measurements of a pq208 package soldered to a typical print ed circuit board. all other results are based on worst-case simulation and an interpolation of the pq208 physical results. 3. if more than one signal standard is assigned to the i/os of a given bank, refer to xapp689 : managing ground bounce in large fpgas for information on how to perform weighted average sso calculations. table 97: recommended number of simultaneously switching outputs per v cco -gnd pair (continued) signal standard (iostandard) package type vq 100 tq 144 pq 208 cp 132 ft256, fg320, fg400, fg484 dc and switching characteristics 138 www.xilinx.com DS312-3 (v3.8) august 26, 2009 product specification r configurable logic block (clb) timing ta bl e 9 8 : clb (slicem) timing symbol description speed grade units -5 -4 min max min max clock-to-output times t cko when reading from the ffx (ffy) flip-flop, the time from the active transition at the clk input to data appearing at the xq (yq) output -0.52 -0.60ns setup times t as time from the setup of data at the f or g input to the active transition at the clk input of the clb 0.46 -0.52 -ns t dick time from the setup of data at the bx or by input to the active transition at the clk input of the clb 1.58 -1.81 -ns hold times t ah time from the active transition at the clk input to the point where data is last held at the f or g input 0 -0 -ns t ckdi time from the active transition at the clk input to the point where data is last held at the bx or by input 0 -0 -ns clock timing t ch the high pulse width of the clb?s clk signal 0.70 -0.80 -ns t cl the low pulse width of the clk signal 0.70 -0.80 -ns f tog toggle frequency (for export control) 0 657 0 572 mhz propagation times t ilo the time it takes for data to travel from the clb?s f (g) input to the x (y) output -0.66 -0.76ns set/reset pulse width t rpw_clb the minimum allowable pulse width, high or low, to the clb?s sr input 1.57 -1.80 -ns notes: 1. the numbers in this table are based on the operating conditions set forth in ta bl e 7 7 . dc and switching characteristics DS312-3 (v3.8) august 26, 2009 www.xilinx.com 139 product specification r ta bl e 9 9 : clb distributed ram swit ching characteristics symbol description -5 -4 units min max min max clock-to-output times t shcko time from the active edge at the clk input to data appearing on the distributed ram output -2.05 -2.35ns setup times t ds setup time of data at the bx or by input before the active transition at the clk input of the distributed ram 0.40 -0.46 -ns t as setup time of the f/g address inputs before the active transition at the clk input of the distributed ram 0.46 -0.52 -ns t ws setup time of the write enable input before the active transition at the clk input of the distributed ram 0.34 -0.40 -ns hold times t dh hold time of the bx, by data inputs after the active transition at the clk input of the distributed ram 0.13 -0.15 -ns t ah, t wh hold time of the f/g address inputs or the write enable input after the active transition at the clk input of the distributed ram 0 -0 -ns clock pulse width t wph , t wpl minimum high or low pulse width at clk input 0.88 -1.01 -ns table 100: clb shift register switching characteristics symbol description -5 -4 units min max min max clock-to-output times t reg time from the active edge at the clk input to data appearing on the shift register output -3.62 -4.16ns setup times t srlds setup time of data at the bx or by input before the active transition at the clk input of the shift register 0.41 -0.46 -ns hold times t srldh hold time of the bx or by data input after the active transition at the clk input of the shift register 0.14 -0.16 -ns clock pulse width t wph , t wpl minimum high or low pulse width at clk input 0.88 -1.01 -ns dc and switching characteristics 140 www.xilinx.com DS312-3 (v3.8) august 26, 2009 product specification r clock buffer/multiplexer switching characteristics table 101: clock distribution swit ching characteristics description symbol maximum units speed grade -5 -4 global clock buffer (bufg, bufgmux, bufgce) i input to o-output delay t gio 1.46 1.46 ns global clock multiplexer (bufgmux) se lect s-input setup to i0 and i1 inputs. same as bufgce enable ce-input t gsi 0.55 0.63 ns frequency of signals distributed on global buffers (all sides) f bufg 333 311 mhz dc and switching characteristics DS312-3 (v3.8) august 26, 2009 www.xilinx.com 141 product specification r 18 x 18 embedded multiplier timing table 102: 18 x 18 embedded multiplier timing symbol description speed grade units -5 -4 minmaxminmax combinatorial delay t mult combinatorial multiplier propagation delay from the a and b inputs to the p outputs, assuming 18-bit inputs and a 36-bit product (areg, breg, and preg registers unused) -4.34 (1) -4.88 (1) ns clock-to-output times t msckp_p clock-to-output delay from the active transition of the clk input to valid data appearing on the p outputs when using the preg register (2) -0.98 -1.10ns t msckp_a t msckp_b clock-to-output delay from the active transition of the clk input to valid data appearing on the p outputs when using either the areg or breg register (3) -4.42 -4.97ns setup times t msdck_p data setup time at the a or b input before the active transition at the clk when using only the preg output register (areg, breg registers unused) (2) 3.54 -3.98 -ns t msdck_a data setup time at the a input before the active transition at the clk when using the areg input register (3) 0.20 -0.23 -ns t msdck_b data setup time at the b input before the active transition at the clk when using the breg input register (3) 0.35 -0.39 -ns hold times t msckd_p data hold time at the a or b input after the active transition at the clk when using only the preg output register (areg, breg registers unused) (2) ? 0.97 - ? 0.97 -ns t msckd_a data hold time at the a input after the active transition at the clk when using the areg input register (3) 0.03 -0.04 -ns t msckd_b data hold time at the b input after the active transition at the clk when using the breg input register (3) 0.04 -0.05 -ns clock frequency f mult internal operating frequency for a two-stage 18x18 multiplier using the areg and breg input registers and the preg output register (1) 02700240mhz notes: 1. combinatorial delay is less and pipelined performance is higher when multiplying input data with less than 18 bits. 2. the preg register is typically used in both single- stage and two-stage pipelined multiplier implementations. 3. input registers areg or breg are typically used when inferring a two-stage multiplier. dc and switching characteristics 142 www.xilinx.com DS312-3 (v3.8) august 26, 2009 product specification r block ram timing table 103: block ram timing symbol description speed grade units -5 -4 min max min max clock-to-output times t bcko when reading from block ram, the delay from the active transition at the clk input to data appearing at the dout output -2.45 -2.82ns setup times t back setup time for the addr inputs before the active transition at the clk input of the block ram 0.33 -0.38 -ns t bdck setup time for data at the din inputs before the active transition at the clk input of the block ram 0.23 -0.23 -ns t beck setup time for the en input before the active transition at the clk input of the block ram 0.67 -0.77 -ns t bwck setup time for the we input before the active transition at the clk input of the block ram 1.09 -1.26 -ns hold times t bcka hold time on the addr inputs after the active transition at the clk input 0.12 -0.14 -ns t bckd hold time on the din inputs af ter the active transition at the clk input 0.12 -0.13 -ns t bcke hold time on the en input after the active transition at the clk input 0 -0 -ns t bckw hold time on the we input after the active transition at the clk input 0 -0 -ns clock timing t bpwh high pulse width of the clk signal 1.39 -1.59 -ns t bpwl low pulse width of the clk signal 1.39 -1.59 -ns clock frequency f bram block ram clock frequency. ram read output value written back into ram, for shift-registers and circular buffers. write-only or read-only performance is faster. 02700230mhz notes: 1. the numbers in this table are based on the operating conditions set forth in ta bl e 7 7 . dc and switching characteristics DS312-3 (v3.8) august 26, 2009 www.xilinx.com 143 product specification r digital clock manager (dcm) timing for specification purposes, the dcm consists of three key components: the delay-locked loop (dll), the digital fre- quency synthesizer (dfs), and the phase shifter (ps). aspects of dll operation play a role in all dcm applica- tions. all such applications inevitably use the clkin and the clkfb inputs connected to either the clk0 or the clk2x feedback, respectively. thus, specifications in the dll tables ( table 104 and ta b l e 1 0 5 ) apply to any application that only employs the dll component. when the dfs and/or the ps components are used together with the dll, then the specifications lis ted in the dfs and ps tables ( ta bl e 1 0 6 through ta bl e 1 0 9 ) supersede any correspond- ing ones in the dll tables. dll specifications that do not change with the addition of dfs or ps functions are pre- sented in ta b l e 1 0 4 and ta b l e 1 0 5 . period jitter and cycle-cycle jitter are two of many different ways of specifying clock jitter. both specifications describe statistical variation from a mean value. period jitter is the worst-case deviation from the ideal clock period over a collection of m illions of samples. in a histo- gram of period jitter, the mean value is the clock period. cycle-cycle jitter is the worst-ca se difference in clock period between adjacent clock cycles in the collection of clock peri- ods sampled. in a histogram of cycle-cycle jitter, the mean value is zero. spread spectrum dcms accept typical spread spectrum clocks as long as they meet the input requirem ents. the dll will track the fre- quency changes created by the spread spectrum clock to drive the global clocks to the fpga logic. see xapp469 , spread-spectrum clocking reception for displays for details. delay-locked loop (dll) table 104: recommended operating conditions for the dll symbol description speed grade units -5 -4 min max min max input frequency ranges f clkin clkin_freq_dll frequency of the clkin clock input stepping 0 xc3s100e xc3s250e xc3s500e xc3s1600e n/a n/a 5 (2) 90 (3) mhz xc3s1200e (3) 200 (3) mhz stepping 1 all 5 (2) 275 (3) 240 (3) mhz input pulse requirements clkin_pulse clkin pulse width as a percentage of the clkin period f clkin < 150 mhz 40% 60% 40% 60% - f clkin > 150 mhz 45% 55% 45% 55% - input clock jitter tolerance and delay path variation (4) clkin_cyc_jitt_dll_lf cycle-to-cycle jitter at the clkin input f clkin < 150 mhz -300 - 300 ps clkin_cyc_jitt_dll_hf f clkin > 150 mhz -150 - 150 ps clkin_per_jitt_dll period jitter at the clkin input -1 -1ns clkfb_delay_var_ext allowable variation of off-chip feedback delay from the dcm output to the clkfb input -1 -1ns notes: 1. dll specifications apply when any of the dll outputs (clk0, cl k90, clk180, clk270, clk2x, clk2x180, or clkdv) are in use. 2. the dfs, when operating independently of the dll, supports lower fclkin frequencies. see ta bl e 1 0 6 . 3. to support double the maximum effective fclkin limit, set the clkin_divide_by_2 attribute to true. this attribute divides the incoming clock frequency by two as it enters the dcm. the clk2x output reproduces the clock frequency provided on the clkin input. 4. clkin input jitter beyond these limits might cause the dcm to lose lock. dc and switching characteristics 144 www.xilinx.com DS312-3 (v3.8) august 26, 2009 product specification r table 105: switching characteristics for the dll symbol description device speed grade units -5 -4 min max min max output frequency ranges clkout_freq_clk0 frequency for the clk0 and clk180 outputs stepping 0 xc3s100e xc3s250e xc3s500e xc3s1600e n/a n/a 5 90 mhz xc3s1200e 200 mhz stepping 1 all 5 275 240 mhz clkout_freq_clk90 frequency for the clk90 and clk270 outputs stepping 0 xc3s100e xc3s250e xc3s500e xc3s1600e n/a n/a 5 90 mhz xc3s1200e 167 mhz stepping 1 all 5 200 200 mhz clkout_freq_2x frequency for the clk2x and clk2x180 outputs stepping 0 xc3s100e xc3s250e xc3s500e xc3s1600e n/a n/a 10 180 mhz xc3s1200e 311 mhz stepping 1 all 10 333 311 mhz clkout_freq_dv frequency for the clkdv output stepping 0 xc3s100e xc3s250e xc3s500e xc3s1600e n/a n/a 0.3125 60 mhz xc3s1200e 133 mhz stepping 1 all 0.3125 183 160 mhz output clock jitter (2,3,4) clkout_per_jitt_0 period jitter at the clk0 output all -100 - 100 ps clkout_per_jitt_90 period jitter at the clk90 output -150 - 150 ps clkout_per_jitt_180 period jitter at the clk180 output -150 - 150 ps clkout_per_jitt_270 period jitter at the clk270 output -150 - 150 ps clkout_per_jitt_2x period jitter at the clk2x and clk2x180 outputs -[1% of clkin period + 150] -[1% of clkin period + 150] ps clkout_per_jitt_dv1 period jitter at the clkdv output when performing integer division -150 - 150 ps clkout_per_jitt_dv2 period jitter at the clkdv output when performing non-integer division -[1% of clkin period + 200] -[1% of clkin period + 200] ps duty cycle (4) clkout_duty_cycle_dll duty cycle variation for the clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv outputs, including the bufgmux and clock tree duty-cycle distortion all -[1% of clkin period + 400] -[1% of clkin period + 400] ps dc and switching characteristics DS312-3 (v3.8) august 26, 2009 www.xilinx.com 145 product specification r phase alignment (4) clkin_clkfb_phase phase offset between the clkin and clkfb inputs all -200 - 200 ps clkout_phase_dll phase offset between dll outputs clk0 to clk2x (not clk2x180) -[1% of clkin period + 100] -[1% of clkin period + 100] ps all others -[1% of clkin period + 200] -[1% of clkin period + 200] ps lock time lock_dll (3) when using the dll alone: the time from deassertion at the dcm?s reset input to the rising transition at its locked output. when the dcm is locked, the clkin and clkfb signals are in phase 5 mhz < f clkin < 15 mhz all -5 -5ms f clkin > 15 mhz -600 - 600 s delay lines dcm_delay_step finest delay resolution all 20 40 20 40 ps notes: 1. the numbers in this table are based on the operating conditions set forth in ta bl e 7 7 and ta bl e 1 0 4 . 2. indicates the maximum amount of output jitter that the dcm adds to the jitter on the clkin input. 3. for optimal jitter tolerance and faster lock time, use the clkin_period attribute. 4. some jitter and duty-cycle s pecifications include 1% of in put clock period or 0.01 ui. example: the data sheet specifies a maximum jitter of "[1% of clkin period + 150]". assume the clkin frequency is 100 mhz. the equivalent clkin period is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. according to the data sheet , the maximum jitter is [100 ps + 150 ps] = 250ps. table 105: switching characteristics for the dll (continued) symbol description device speed grade units -5 -4 min max min max dc and switching characteristics 146 www.xilinx.com DS312-3 (v3.8) august 26, 2009 product specification r digital frequency synthesizer (dfs) table 106: recommended operating conditions for the dfs symbol description speed grade units -5 -4 min max min max input frequency ranges (2) f clkin clkin_freq_fx frequency for the clkin input 0.200 333 (4) 0.200 333 (4) mhz input clock jitter tolerance (3) clkin_cyc_jitt_fx_lf cycl e-to-cycle jitter at the clkin input, based on clkfx output frequency f clkfx < 150 mhz -300 -300ps clkin_cyc_jitt_fx_hf f clkfx > 150 mhz -150 -150ps clkin_per_jitt_fx period jitter at the clkin input -1 -1ns notes: 1. dfs specifications apply when either of the dfs outputs (clkfx or clkfx180) are used. 2. if both dfs and dll outputs are used on the same dcm, follow the more restrictive clkin_freq_dll specifications in ta bl e 1 0 4 . 3. clkin input jitter beyond these limits may cause the dcm to lose lock. 4. to support double the maximum effective fclkin limit, set the clkin_divide_by_2 attribute to true. this attribute divides the incoming clock frequency by two as it enters the dcm. table 107: switching characteristics for the dfs symbol description device speed grade units -5 -4 min max min max output frequency ranges clkout_freq_fx_lf frequency for the clkfx and clkfx180 outputs, low frequencies stepping 0 xc3s100e xc3s250e xc3s500e xc3s1600e n/a n/a 5 90 mhz clkout_freq_fx_hf frequency for the clkfx and clkfx180 outputs, high frequencies 220 307 mhz clkout_freq_fx frequency for the clkfx and clkfx180 outputs stepping 0 xc3s1200e 5 307 mhz stepping 1 all 5 333 311 mhz output clock jitter (2,3) clkout_per_jitt_fx period jitter at the clkfx and clkfx180 outputs. all typ max typ max clkin 20 mhz note 6 ps clkin > 20 mhz [1% of clkfx period + 100] [1% of clkfx period + 200] [1% of clkfx period + 100] [1% of clkfx period + 200] ps duty cycle (4,5) clkout_duty_cycle_fx duty cycle prec ision for the clkfx and clkfx180 outputs, including the bufgmux and clock tree duty-cycle distortion all -[1% of clkfx period + 400] -[1% of clkfx period + 400] ps phase alignment (5) clkout_phase_fx phase offset between the dfs clkfx output and the dll clk0 output when both the dfs and dll are used all - 200 -200ps clkout_phase_fx180 phase offset between the dfs clkfx180 output and the dll clk0 output when both the dfs and dll are used all -[1% of clkfx period + 300] -[1% of clkfx period + 300] ps dc and switching characteristics DS312-3 (v3.8) august 26, 2009 www.xilinx.com 147 product specification r phase shifter (ps) lock time lock_fx (2) the time from deassertion at the dcm?s reset input to the rising transition at its locked output. the dfs asserts locked when the clkfx and clkfx180 signals are valid. if using both the dll and the dfs, use the longer locking time. 5 mhz < f clkin < 15 mhz all -5 -5ms f clkin > 15 mhz - 450 - 450 s notes: 1. the numbers in this table are based on the operating conditions set forth in ta bl e 7 7 and ta bl e 1 0 6 . 2. for optimal jitter tolerance and faster lock time, use the clkin_period attribute. 3. maximum output jitter is characterized within a reasonable nois e environment (150 ps input period jitter, 40 ssos and 25% clb switching). output jitter strongly depends on the environment, including the number of ssos, the output drive strength, clb utilization, clb switching activities, switching frequency, powe r supply and pcb design. the actual maximum output jitter depen ds on the system application. 4. the clkfx and clkfx180 outputs alwa ys have an approximate 50% duty cycle. 5. some duty-cycle and alignment s pecifications include 1% of the clkfx output period or 0.01 ui. example: the data sheet specifies a maximum jitter of "[1% of clkfx period + 300]". assume t he clkfx output frequency is 100 mhz. the equivalent clkfx period is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. according to the data sheet, the maximum jitter is [100 ps + 300 ps] = 400 ps. 6. use the spartan-3a jitter calculator ( www.xilinx.com/support/documentation/data_sheets/s3a_jitter_calc.zip ) to estimate dfs output jitter. use the clocking wizard to determine jitter for a specific design. table 107: switching characteristics for the dfs (continued) symbol description device speed grade units -5 -4 min max min max table 108: recommended operating conditions for the ps in variable phase mode symbol description speed grade units -5 -4 min max min max operating frequency ranges psclk_freq (f psclk ) frequency for the psclk input 1 167 1 167 mhz input pulse requirements psclk_pulse psclk pulse width as a percentage of the psclk period 40% 60% 40% 60% - table 109: switching characteristics for the ps in variable phase mode symbol description equation units phase shifting range max_steps (2) maximum allowed number of dcm_delay_step steps for a given clkin clock period, where t = clkin clock period in ns. if using clkin_divide_by_2 = true, double the effective clock period. clkin < 60 mhz [integer(10 ? (t clkin ? 3 ns))] steps clkin > 60 mhz [integer(15 ? (t clkin ? 3 ns))] steps fine_shift_range_min minimum guaranteed delay for variable phase shifting [max_steps ? dcm_delay_step_min] ns fine_shift_range_max maximum guaranteed delay for variable phase shifting [max_steps ? dcm_delay_step_max] ns dc and switching characteristics 148 www.xilinx.com DS312-3 (v3.8) august 26, 2009 product specification r notes: 1. the numbers in this table are based on the operating conditions set forth in ta bl e 7 7 and ta b l e 1 0 8 . 2. the maximum variable phase shift range, max_steps, is only vali d when the dcm is has no initial fixed phase shifting, i.e., t he phase_shift attribute is set to 0. 3. the dcm_delay_step values are provided at the bottom of table 105 . table 109: switching characteristics for the ps in variable phase mode (continued) symbol description equation units dc and switching characteristics DS312-3 (v3.8) august 26, 2009 www.xilinx.com 149 product specification r miscellaneous dcm timing table 110: miscellaneous dcm timing symbol description min max units dcm_rst_pw_min (1) minimum duration of a rst pulse width 3 -clkin cycles dcm_rst_pw_max (2) maximum duration of a rst pulse width n/a n/a seconds n/a n/a seconds dcm_config_lag_time (3) maximum duration from v ccint applied to fpga configuration successfully completed (done pin goes high) and clocks applied to dcm dll n/a n/a minutes n/a n/a minutes notes: 1. this limit only applies to applications that use the dcm dll outputs (clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv ). the dcm dfs outputs (clkfx, clkfx180) are unaffected. 2. this specification is equivalent to the virtex-4 dcm_reset s pecfication.this specification does not apply for spartan-3e fpga s. 3. this specification is equivalent to the virtex-4 tconfig specification. this specification does not apply for spartan-3e fpga s. dc and switching characteristics 150 www.xilinx.com DS312-3 (v3.8) august 26, 2009 product specification r configuration and jtag timing general configuration power-on/reconfigure timing figure 74: waveforms for power-on and the beginning of configuration table 111: power-on timing and the beginning of configuration symbol description device all speed grades units min max t por (2) the time from the application of v ccint , v ccaux , and v cco bank 2 supply voltage ramps (whichever occurs last) to the rising transition of the init_b pin xc3s100e - 5 ms xc3s250e - 5 ms xc3s500e - 5 ms xc3s1200e - 5 ms xc3s1600e - 7 ms t prog the width of the low-going pulse on the prog_b pin all 0.5 - s t pl (2) the time from the rising edge of the prog_b pin to the rising transition on the init_b pin xc3s100e -0.5ms xc3s250e -0.5ms xc3s500e -1ms xc3s1200e -2ms xc3s1600e -2ms t init minimum low pulse width on init_b output all 250 -ns t icck (3) the time from the rising edge of the init_b pin to the generation of the configuration clock signal at the cclk output pin all 0.5 4.0 s notes: 1. the numbers in this table are based on the operating conditions set forth in ta bl e 7 7 . this means power must be applied to all v ccint , v cco , and v ccaux lines. 2. power-on reset and the clearing of configuration memory occurs during this period. 3. this specification applies only to the mast er serial, spi, bpi-up , and bpi-down modes. v cci n t (supply) (supply) (supply) v ccaux v cco bank 2 prog_b (output) (open-drain) (input) i n it_b cclk DS312-3_01_103105 1.2 v 2.5 v t icck t prog t pl t por 1.0 v 1.0 v 2.0 v notes: 1. the v ccint , v ccaux , and v cco supplies may be applied in any order. 2. the low-going pulse on prog_b is optional after power-on but necessary for reconfiguration without a power cycle. 3. the rising edge of init_b samples the voltage levels applied to the mode pins (m0 - m2). dc and switching characteristics DS312-3 (v3.8) august 26, 2009 www.xilinx.com 151 product specification r configuration clock (cclk) characteristics table 112: master mode cclk output period by configrate option setting symbol description configrate setting temperature range minimum maximum units t cclk1 cclk clock period by configrate setting 1 (power-on value and default value) commercial 570 1,250 ns industrial 485 ns t cclk3 3 commercial 285 625 ns industrial 242 ns t cclk6 6 commercial 142 313 ns industrial 121 ns t cclk12 12 commercial 71.2 157 ns industrial 60.6 ns t cclk25 25 commercial 35.5 78.2 ns industrial 30.3 ns t cclk50 50 commercial 17.8 39.1 ns industrial 15.1 ns notes: 1. set the configrate option value when generating a configuration bitstream. see bitstream generator (bitgen) options in module 2. table 113: master mode cclk output frequency by configrate option setting symbol description configrate setting temperature range minimum maximum units f cclk1 equivalent cclk clock frequency by configrate setting 1 (power-on value and default value) commercial 0.8 1.8 mhz industrial 2.1 mhz f cclk3 3 commercial 1.6 3.6 mhz industrial 4.2 mhz f cclk6 6 commercial 3.2 7.1 mhz industrial 8.3 mhz f cclk12 12 commercial 6.4 14.1 mhz industrial 16.5 mhz f cclk25 25 commercial 12.8 28.1 mhz industrial 33.0 mhz f cclk50 50 commercial 25.6 56.2 mhz industrial 66.0 mhz table 114: master mode cclk output minimum low and high time symbol description configrate setting units 136122550 t mccl, t mcch master mode cclk minimum low and high time commercial 276 138 69 34.5 17.1 8.5 ns industrial 235 117 58 29.3 14.5 7.3 ns dc and switching characteristics 152 www.xilinx.com DS312-3 (v3.8) august 26, 2009 product specification r table 115: slave mode cclk input low and high time symbol description min max units t sccl, t scch cclk low and high time 5 ns dc and switching characteristics DS312-3 (v3.8) august 26, 2009 www.xilinx.com 153 product specification r master serial and slave serial mode timing figure 75: waveforms for master serial and slave serial configuration table 116: timing for the master serial and slave serial configuration modes symbol description slave/ master all speed grades units min max clock-to-output times t cco the time from the falling transition on the cclk pin to data appearing at the dout pin both 1.5 10.0 ns setup times t dcc the time from the setup of data at the din pin to the active edge of the cclk pin both 11.0 -ns hold times t ccd the time from the active edge of the cclk pin to the point when data is last held at the din pin both 0 -ns clock timing t cch high pulse width at the cclk input pin master see ta b l e 1 1 4 slave see ta b l e 1 1 5 t ccl low pulse width at the cclk input pin master see ta b l e 1 1 4 slave see ta b l e 1 1 5 f ccser frequency of the clock signal at the cclk input pin no bitstream compression slave 0 66 (2) mhz with bitstream compression 0 20 mhz notes: 1. the numbers in this table are based on the operating conditions set forth in ta bl e 7 7 . 2. for serial configuration with a daisy-chain of multiple fpgas, the maximum limit is 25 mhz. DS312-3_05_103105 bit 0 bit 1 bit n bit n+1 bit n-64 bit n-63 1/f ccser t sccl t dcc t ccd t scch t cco prog_b (input) din (input) dout (output) (open-drain) init_b (input/output) cclk t mccl t mcch dc and switching characteristics 154 www.xilinx.com DS312-3 (v3.8) august 26, 2009 product specification r slave parallel mode timing figure 76: waveforms for slave parallel configuration table 117: timing for the slave parallel configuration mode symbol description all speed grades units min max clock-to-output times t smckby the time from the rising transition on the cclk pin to a signal transition at the busy pin -12.0ns setup times t smdcc the time from the setup of data at the d0-d7 pins to the active edge the cclk pin 11.0 -ns t smcscc setup time on the csi_b pin before the active edge of the cclk pin 10.0 -ns t smccw (2) setup time on the rdwr_b pin before active edge of the cclk pin 23.0 -ns DS312-3_02_103105 byte 0 byte 1 byte n busy high-z high-z byte n+1 t smwcc 1/f ccpar t smcccs t smckby t smckby t scch t smccw t smccd t smcscc t smdcc prog_b (input) (open-drain) init_b (input) csi_b (output) busy rdwr_b (input) (input) cclk (inputs) d0 - d7 t mcch t sccl t mccl notes: 1. it is possible to abort configuration by pulling csi_b low in a given cclk cycle, then switching rdwr_b low or high in any su bsequent cycle for which csi_b remains low. the rdwr_b pin asynchronously controls the driver impedance of the d0 - d7 bus. when rdwr_b switches high, be careful to avoid contention on the d0 - d7 bus. dc and switching characteristics DS312-3 (v3.8) august 26, 2009 www.xilinx.com 155 product specification r hold times t smccd the time from the active edge of the cclk pin to the point when data is last held at the d0-d7 pins 1.0 -ns t smcccs the time from the active edge of the cclk pin to the point when a logic level is last held at the cso_b pin 0 -ns t smwcc the time from the active edge of the cclk pin to the point when a logic level is last held at the rdwr_b pin 0 -ns clock timing t cch the high pulse width at the cclk input pin 5 -ns t ccl the low pulse width at the cclk input pin 5 -ns f ccpar frequency of the clock signal at the cclk input pin no bitstream compression not using the busy pin (2) 050mhz using the busy pin 0 66 mhz with bitstream compression 0 20 mhz notes: 1. the numbers in this table are based on the operating conditions set forth in ta bl e 7 7 . 2. in the slave parallel mode, it is necessary to use the busy pin when the cclk frequency exceeds this maximum specification. 3. some xilinx documents refer to parallel modes as ?selectmap? modes. table 117: timing for the slave parallel configuration mode (continued) symbol description all speed grades units min max dc and switching characteristics 156 www.xilinx.com DS312-3 (v3.8) august 26, 2009 product specification r serial peripheral interface (spi) configuration timing figure 77: waveforms for serial peripheral interface (spi) configuration table 118: timing for serial peripheral interface (spi) configuration mode symbol description minimum maximum units t cclk1 initial cclk clock period see table 112 t cclk n cclk clock period after fpga loads configrate setting see table 112 t minit setup time on vs[2:0] and m[2:0] mode pins before the rising edge of init_b 50 -ns t initm hold time on vs[2:0] and m[2:0]mode pins after the rising edge of init_b 0 -ns t cco mosi output valid after cclk edge see table 116 t dcc setup time on din data input before cclk edge see table 116 t ccd hold time on din data input after cclk edge see table 116 t dh t d s u comm a nd (m sb ) t v t c ss <1:1:1> init_b m[2:0] t minit t initm din cclk (inp u t) t cclk n t cclk1 vs[2:0] (inp u t) new configrate a ctive mode inp u t pin s m[2:0] a nd v a ri a nt s elect inp u t pin s v s [2:0] a re sa mpled when init_b goe s high. after thi s point, inp u t v a l u e s do not m a tter u ntil done goe s high, a t which point the s e pin s b ecome us er-i/o pin s . <0:0:1> pin initi a lly p u lled high b y intern a l p u ll- u p re s i s tor if h s wap inp u t i s low. pin initi a lly high-imped a nce (hi-z) if h s wap inp u t i s high. extern a l p u ll- u p re s i s tor req u ired on c s o_b. t cclk1 t mccl n t mcch n (inp u t) d a t a d a t a d a t a d a t a cso_b mosi t cco t mccl1 t mcch1 t dcc t ccd (inp u t) prog_b hswap (inp u t) h s wap m us t b e s t ab le b efore init_b goe s high a nd con s t a nt thro u gho u t the config u r a tion proce ss . d s3 12- 3 _06_110206 (open-dr a in) s h a ded v a l u e s indic a te s pecific a tion s on a tt a ched s pi fl as h prom. comm a nd (m sb -1) dc and switching characteristics DS312-3 (v3.8) august 26, 2009 www.xilinx.com 157 product specification r table 119: configuration timing requirements for attached spi serial flash symbol description requirement units t ccs spi serial flash prom chip-select time ns t dsu spi serial flash prom data input setup time ns t dh spi serial flash prom data input hold time ns t v spi serial flash prom data clock-to-output time ns f c or f r maximum spi serial flash prom clock frequency (also depends on specific read command used) mhz notes: 1. these requirements are for successful fpga configuration in sp i mode, where the fpga provides the cclk frequency. the post configuration timing can be different to support the specific needs of the application loaded into the fpga and the resulting c lock source. 2. subtract additional printed circuit board routing delay as required by the application. t ccs t mccl1 t cco ? ? ? () ---------------- -------------- - dc and switching characteristics 158 www.xilinx.com DS312-3 (v3.8) august 26, 2009 product specification r byte peripheral interface (bpi) configuration timing figure 78: waveforms for byte-wide peripheral interface (bpi) configuration (bpi-dn mode shown) table 120: timing for byte-wide peripheral interface (bpi) configuration mode symbol description minimum maximum units t cclk1 initial cclk clock period see ta b l e 1 1 2 t cclk n cclk clock period after fpga loads configrate setting see ta b l e 1 1 2 t minit setup time on csi_b, rdwr_b, and m[2:0] mode pins before the rising edge of init_b 50 -ns t initm hold time on csi_b, rdwr_b, and m[2:0] mode pins after the rising edge of init_b 0 -ns t initaddr minimum period of initial a[23:0] address cycle; ldc[2:0] and hdc are asserted and valid bpi-up: (m[2:0]=<0:1:0>) 55t cclk1 cycles bpi-dn: (m[2:0]=<0:1:1>) 22 t cco address a[23:0] outp uts valid after cclk falling edge see ta b l e 1 1 6 t dcc setup time on d[7:0] data inputs before cclk rising edge see ta b l e 1 1 6 t ccd hold time on d[7:0] data inputs after cclk rising edge see ta b l e 1 1 6 (inp u t) hs w ap m u st b e sta b le b efore i n it_b goes high and constant thro u gho u t the config u ration process. data data data address data address byte 0 000_0000 init_b <0:1:0> m[2:0] t mi n it t i n itm ldc[2:0] hdc cso_b byte 1 000_0001 cclk a[23:0] d[7:0] t dcc t ccd t a v q v t cclk1 (inp u t) t i n itaddr t cclk n t cclk1 t cco hswap n e w configrate acti v e pin initially p u lled high b y internal p u ll- u p resistor if hs w ap inp u t is lo w . pin initially high-impedance (hi-z) if hs w ap inp u t is high. mode inp u t pins m[2:0] are sampled w hen i n it_b goes high. after this point, inp u t v al u es do not matter u ntil do n e goes high, at w hich point the mode pins b ecome u ser-i/o pins. (inp u t) prog_b (inp u t) DS312-3_0 8 _032409 (open-drain) shaded v al u es indicate specifications on attached parallel n or flash prom. address dc and switching characteristics DS312-3 (v3.8) august 26, 2009 www.xilinx.com 159 product specification r table 121: configuration timing requirements for attached parallel nor flash symbol description requirement units t ce (t elqv ) parallel nor flash prom chip-select time ns t oe (t glqv ) parallel nor flash prom output-enable time ns t acc (t avqv ) parallel nor flash prom read access time ns t byte (t flqv, t fhqv ) for x8/x16 proms only: byte# to output valid time (3) ns notes: 1. these requirements are for successful fpga configuration in bp i mode, where the fpga provides the cclk frequency. the post configuration timing can be different to support the specific needs of the application loaded into the fpga and the resulting c lock source. 2. subtract additional printed circuit board routing delay as required by the application. 3. the initial byte# timing can be extended using an external, appropriately sized pull-down resistor on the fpga?s ldc2 pin. th e resistor value also depends on whether the fpga?s hswap pin is high or low. table 122: multiboot trigger (mbt) timing symbol description minimum maximum units t mbt multiboot trigger (mbt) low pulse width required to initiate multiboot reconfiguration 300 ns notes: 1. multiboot re-configuration starts on the rising edge after mbt is low for at least the prescribed minimum period. t ce t initaddr () t cco t dcc pcb ? ? ? dc and switching characteristics 160 www.xilinx.com DS312-3 (v3.8) august 26, 2009 product specification r ieee 1149.1/1553 jtag test access port timing figure 79: jtag waveforms tck t tmstck tms tdi tdo (inp u t) (inp u t) (inp u t) (o u tp u t) t tcktms t tcktdi t tcktdo t tditck DS312-3_79_032409 t cch t ccl 1/f tck table 123: timing for the jtag test access port symbol description all speed grades units min max clock-to-output times t tcktdo the time from the falling tr ansition on the tck pin to data appearing at the tdo pin 1.0 11.0 ns setup times t tditck the time from the setup of data at the tdi pin to the rising transition at the tck pin 7.0 -ns t tmstck the time from the setup of a logic level at the tms pin to the rising transition at the tck pin 7.0 -ns hold times t tcktdi the time from the rising transition at the tck pin to the point when data is last held at the tdi pin 0 -ns t tcktms the time from the rising transition at the tck pin to the point when a logic le vel is last held at the tms pin 0 -ns clock timing t cch the high pulse width at the tck pin 5 -ns t ccl the low pulse width at the tck pin 5 -ns f tck frequency of the tck signal -30mhz notes: 1. the numbers in this table are based on the operating conditions set forth in ta bl e 7 7 . dc and switching characteristics DS312-3 (v3.8) august 26, 2009 www.xilinx.com 161 product specification r revision history the following table shows the revision history for this document. date version revision 03/01/05 1.0 initial xilinx release. 11/23/05 2.0 added ac timing information and additional dc specifications. 03/22/06 3.0 upgraded data sheet status to preliminary. finalized production timing parameters. all speed grades for all spartan-3e fpgas are now production status using the v1.21 speed files, as shown in ta b l e 8 4 . expanded description in note 2, ta b l e 7 8 . updated pin-to-pin and clock-to-output timing based on final characterization, shown in ta b l e 8 6 . updated system-synchronous input setup and hold times based on final characterization, shown in ta b l e 8 7 and ta bl e 8 8 . updated other i/o timing in ta b l e 9 0 . provided input and output adjustments for lvpecl_25, diff_sstl and diff_hstl i/o standards that supersede the v1.21 speed file values, in ta bl e 9 1 and ta b l e 9 4 . reduced i/o three-state and set/reset delays in ta bl e 9 3 . added xc3s100e fpga in cp132 package to ta bl e 9 6 . increased t as slice flip-flop timing by 100 ps in ta b l e 9 8 . updated distributed ram timing in ta b l e 9 9 and srl16 timing in ta bl e 1 0 0 . updated global clock timing, removed left/right clock buffer limits in table 101 . updated block ram timing in ta bl e 1 0 3 . added dcm parameters for remainder of step 0 device; added improved step 1 dcm performance to ta b l e 1 0 4 , ta b l e 1 0 5 , ta b l e 1 0 6 , and ta bl e 1 0 7 . added minimum init_b pulse width specification, t init , in ta bl e 1 1 1 . increased data hold time for slave parallel mode to 1.0 ns (t smccd ) in ta b l e 1 1 7 . improved the dcm performance for the xc3s1200e, stepping 0 in ta b l e 1 0 4 , ta b l e 1 0 5 , ta b l e 1 0 6 , and ta bl e 1 0 7 . corrected links in ta bl e 1 1 8 and ta bl e 1 2 0 . added multiboot timing specifications to ta b l e 1 2 2 . 04/07/06 3.1 improved sso limits for lvds_25, mini_lvds_25, and rsds_25 i/o standards in the qfp packages ( ta bl e 9 7 ). removed potentially confusing note 2 from ta b l e 7 8 . 05/19/06 3.2 clarified that 100 mv of hysteresis applies to lvcmos33 and lvcmos25 i/o standards (note 4, ta bl e 8 0 ). other minor edits. 05/30/06 3.2.1 corrected various typos and incorrect links. 11/09/06 3.4 improved absolute maximum voltage specifications in ta b l e 7 3 , providing additional overshoot allowance. widened the recommended voltage range for pci and pci-x standards in ta b l e 8 0 . clarified note 2, ta bl e 8 3 . improved various timing specifications for v1.26 speed file. added ta b l e 8 5 to summarize the history of speed file releases after which time all devices became production status. added absolute minimum values for ta bl e 8 6 , ta b l e 9 2 , and ta b l e 9 3 . updated pin-to-pin setup and hold timing based on default ifd_delay_value settings in ta b l e 8 7 , ta b l e 8 8 , and ta b l e 9 0 . added ta b l e 8 9 about source-synchronous input capture sample window. promoted module 3 to production status. synchronized all modules to v3.4. 03/16/07 3.5 based on extensive 90 nm production data, improved (reduced) the maximum quiescent current limits for the i ccintq , i ccauxq , and i ccoq specifications in ta b l e 7 9 by an average of 50%. 05/29/07 3.6 added note to ta b l e 7 4 and ta b l e 7 5 regarding hswap in step 0 devices. updated t rpw_clb in ta bl e 9 8 to match value in speed file. improved clkout_freq_clk90 to 200 mhz for stepping 1 in ta b l e 1 0 5 . dc and switching characteristics 162 www.xilinx.com DS312-3 (v3.8) august 26, 2009 product specification r 04/18/08 3.7 clarified that stepping 0 was offered only for -4c and removed stepping 0 -5 specifications. added reference to xapp459 in ta b l e 7 3 and ta bl e 7 7 . improved recommended max v cco to 3.465v (3.3v + 5%) in ta b l e 7 7 . removed minimum input capacitance from ta b l e 7 8 . updated recommended operating conditions for lvcmos and pci i/o standards in ta b l e 8 0 . removed absolute minimums from ta bl e 8 6 , ta bl e 9 2 and ta b l e 9 3 and added footnote recommending use of timing analyzer for minimum values. updated t psfd and t phfd in ta b l e 8 7 to match current speed file. update t rpw_iob in ta b l e 8 8 to match current speed file and clb equivalent spec. added xc3s500e vqg100 to ta bl e 9 6 . replaced t mulckid with t msckd for a, b, and p registers in table 102 . updated clkout_per_jitt_fx in ta b l e 1 0 7 . updated max_steps equation in ta bl e 1 0 9 . updated figure 78 and ta b l e 1 2 0 to correct cclk active edge. updated links. 08/26/09 3.8 added refe rence to xapp459 in ta b l e 7 3 note 2. updated bpi timing in figure 78 , ta b l e 1 1 9 , and ta bl e 1 2 0 . removed v ref requirements for differential hstl and differential sstl in ta bl e 9 5 . added spread spectrum paragraph. revised hold times for t ioickpd in ta b l e 8 8 and setup times for t dick in ta bl e 9 8 . added note 4 to ta bl e 1 0 6 and note 6 to ta b l e 1 0 7 , and updated note 6 for table 107 to add input jitter. date version revision DS312-4 (v3.8) august 26, 2009 www.xilinx.com 163 product specification ? 2005?2009 xilinx, inc. xilinx, the xilinx logo, virtex, spartan, ise, and other designated brands included herein are tradema rks of xilinx in the united states and other coun- tries. all other trademarks are the property of their respective owners. introduction this section describes the various pins on a spartan?-3e fpga and how they connect within the supported compo- nent packages. pin types most pins on a spartan-3e fpga are general-purpose, user-defined i/o pins. there are, however, up to 11 different functional types of pins on spartan-3e packages, as out- lined in ta b l e 1 2 4 . in the package footprint drawings that fol- low, the individual pins are color-coded according to pin type as in the table. 233 spartan-3e fpga family: pinout descriptions DS312-4 (v3.8) august 26, 2009 0 product specification r table 124: types of pins on spartan-3e fpgas type / color code description pin name(s) in type i/o unrestricted, general-purpose user-i/o pin. most pins can be paired together to form differential i/os. io io_lxxy_# input unrestricted, general-purpose input-only pin. this pin does not have an output structure, differential termination resistor, or pci clamp diode. ip ip_lxxy_# dual dual-purpose pin used in some configuration modes during the configuration process and then usually available as a user i/o after configuration. if the pin is not used during configuration, this pin behaves as an i/o-type pin. some of the dual-purpose pins are also shared with bottom-edge global (gclk) or right-half (rhclk) clock inputs. see the configuration section in module 2 for additional information on these signals. m[2:0] hswap cclk mosi/csi_b d[7:1] d0/din cso_b rdwr_b busy/dout init_b a[23:20] a19/vs2 a18/vs1 a17/vs0 a[16:0] ldc[2:0] hdc vref dual-purpose pin that is either a user -i/o pin or input-only pin, or, along with all other vref pins in the same bank, provides a reference voltage input for certain i/o standards. if used for a reference voltage within a bank, all vref pins within the bank must be connected. ip/vref_# ip_lxxy_#/vref_# io/vref_# io_lxxy_#/vref_# clk either a user-i/o pin or input-only pin, or an input to a specific clock buffer driver. every package has 16 global clock inputs that optionally clock the entire device. the rhclk inputs optionally clock the right-half of the device. the lhclk inputs optionally clock the left-half of the device. some of the clock pins are shared with the dual-purpose configuration pins and are considered dual-type. see the clocking infrastructure section in module 2 for additional information on these signals. io_lxxy_#/gclk[15:10, 7:2] ip_lxxy_#/gclk[9:8, 1:0] io_lxxy_#/lhclk[7:0] io_lxxy_#/rhclk[7:0] pinout descriptions 164 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r differential pair labeling i/os with lxxy_# are part of a differential pair. ?l? indicates differential capabilit y. the ?xx? field is a two-digit integer, unique to each bank that identifies a differential pin-pair. the ?y? field is either ?p? for the true signal or ?n? for the inverted signal in the differential pair. the ?#? field is the i/o bank number. the pin name suffix has the following significance. figure 80 provides a specific example showing a differential input to and a differential output from bank 1. ?l? indicates that the pin is part of a differential pair. "xx" is a two-digit integer, unique for each bank, that identifies a differential pin-pair. ?y? is replaced by ?p? for the true signal or ?n? for the inverted. these two pins form one differential pin-pair. ?#? is an integer, 0 through 3, indicating the associated i/o bank. config dedicated configuration pin. not available as a user-i/o pin. every package has two dedicated configuration pins. these pins are powered by vccaux. see the configuration section in module 2 for details. done, prog_b jtag dedicated jtag pin. not available as a user-i/o pin. every package has four dedicated jtag pins. these pins are powered by vccaux. tdi, tms, tck, tdo gnd dedicated ground pin. the number of gnd pins depends on the package used. all must be connected. gnd vccaux dedicated auxiliary power supply pi n. the number of vccaux pins depends on the package used. all must be connected to +2.5v. see the powering spartan-3e fpgas section in module 2 for details. vccaux vccint dedicated internal core logic power supply pin. the number of vccint pins depends on the package used. all must be connected to +1.2v. see the powering spartan-3e fpgas section in module 2 for details. vccint vcco along with all the other vcco pins in the same bank, this pin supplies power to the output buffers within the i/o bank and sets the input threshold voltage for some i/o standards. see the powering spartan-3e fpgas section in module 2 for details. vcco_# n.c. this package pin is not connected in this specific device/package combination but may be connected in larger devices in the same package. n.c. notes: 1. # = i/o bank number, an integer between 0 and 3. 2. irdy/trdy designations are for pci designs; refer to pci documentation for details. table 124: types of pins on spartan-3e fpgas (continued) type / color code description pin name(s) in type figure 80: differential pair labeling io_l3 8 p_1 io_l3 8n _1 io_l39p_1 io_l39 n _1 spartan-3e fpga DS312-4_00_032409 pair nu m b er bank nu m b er positi v e polarity tr u e recei v er n egati v e polarity in v erted recei v er bank 1 bank 0 bank 2 bank 3 pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 165 product specification r package overview table 125 shows the eight low-cost, space-saving produc- tion package styles for the spartan-3e family. each pack- age style is available as a standard and an environmentally friendly lead-free (pb-free) option. the pb-free packages include an extra ?g? in the package style name. for exam- ple, the standard ?vq100? package becomes ?vqg100? when ordered as the pb-free option. the mechanical dimensions of the standard and pb-free packages are simi- lar, as shown in the mechanical drawings provided in ta b l e 1 2 7 . not all spartan-3e densities are available in all packages. for a specific package, however, there is a common foot- print that supports all the devices available in that package. see the footprint diagrams that follow. for additional package information, see ug112 : device package user guide . selecting the right package option spartan-3e fpgas are available in both quad-flat pack (qfp) and ball grid array (bga) packaging options. while qfp packaging offers the lowest absolute cost, the bga packages are superior in almost every other aspect, as summarized in table 126 . consequently, xilinx recom- mends using bga packaging whenever possible. table 125: spartan-3e family package options package leads type maximum i/o lead pitch (mm) footprint area (mm) height (mm) mass (1) (g) vq100 / vqg100 100 very-thin quad fl at pack (vqfp) 66 0.5 16 x 16 1.20 0.6 cp132 / cpg132 132 chip-scale package (csp) 92 0.5 8.1 x 8.1 1.10 0.1 tq144 / tqg144 144 thin quad flat pack (tqfp) 108 0.5 22 x 22 1.60 1.4 pq208 / pqg208 208 plastic quad flat pack (pqfp) 158 0.5 30.6 x 30.6 4.10 5.3 ft256 / ftg256 256 fine-pitch, thin ball grid array (fbga) 190 1.0 17 x 17 1.55 0.9 fg320 / fgg320 320 fine-pitch ball gr id array (fbga) 250 1.0 19 x 19 2.00 1.4 fg400 / fgg400 400 fine-pitch ball gr id array (fbga) 304 1.0 21 x 21 2.43 2.2 fg484 / fgg484 484 fine-pitch ball gr id array (fbga) 376 1.0 23 x 23 2.60 2.2 notes: 1. package mass is 10%. table 126: qfp and bga comparison characteristic quad flat pack (qfp) ball grid array (bga) maximum user i/o 158 376 packing density (logic/area) good better signal integrity fair better simultaneous switching output (sso) support fair better thermal dissipation fair better minimum printed circuit board (pcb) layers 4 4-6 hand assembly/rework possible difficult pinout descriptions 166 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r mechanical drawings detailed mechanical drawings for each package type are available from the xilinx? web site at the specified location in table 127 . material declaration data sheets (mdds) are also avail- able on the xilinx web site for each package. package pins by type each package has three separate voltage supply inputs?vccint, vccaux, and vcco?and a common ground return, gnd. the numbers of pins dedicated to these functions vary by package, as shown in ta b l e 1 2 8 . a majority of package pins are user-defined i/o or input pins. however, the numbers and characteristics of these i/o depend on the device type and the package in which it is available, as shown in ta bl e 1 2 9 . the table shows the max- imum number of single-ended i/o pins available, assuming that all i/o -, input -, dual -, vref -, and clk -type pins are used as general-purpose i/o. likewise, the table shows the maximum number of differential pin-pairs available on the package. finally, the table shows how the total maximum user-i/os are distributed by pin type, including the number of unconnected?i.e., n.c.?pins on the device. table 127: xilinx package mechanical drawings and material declaration data sheets package package drawing mdds vq100 package drawing pk173_vq100 vqg100 pk130_vqg100 cp132 package drawing pk147_cp132 cpg132 pk101_cpg132 tq144 package drawing pk169_tq144 tqg144 pk126_tqg144 pq208 package drawing pk166_pq208 pqg208 pk123_pqg208 ft256 package drawing pk158_ft256 ftg256 pk115_ftg256 fg320 package drawing pk152_fg320 fgg320 pk106_fgg320 fg400 package drawing pk182_fg400 fgg400 pk108_fgg400 fg484 package drawing pk183_fg484 fgg484 pk110_fgg484 table 128: power and ground supply pins by package package vccint vccaux vcco gnd vq100 4 4 8 12 cp132 6 4 8 16 tq144 4 4 9 13 pq208 4 8 12 20 ft256 8 8 16 28 fg320 8 8 20 28 fg400 16 8 24 42 fg484 16 10 28 48 pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 167 product specification r electronic versions of the package pinout tables and foot- prints are available for down load from the xilinx website. download the files from t he following location: using a spreadsheet program, the data can be sorted and reformat- ted according to any specific needs. similarly, the ascii-text file is easily parsed by most scripting programs. http://www.xilinx.com/ support/documentation/data_sheets/ s3e_pin.zip table 129: maximum user i/o by package device package maximum user i/os and input-only maximum input- only maximum differential pairs all possible i/os by type i/o input dual vref (1 ) clk (2) n.c. xc3s100e vq100 66 7 30 16 1 21 4 24 0 xc3s250e 66 7 30 16 1 21 4 24 0 xc3s500e 66 7 30 16 1 21 4 24 0 xc3s100e cp132 83 11 35 16 2 42 7 16 9 xc3s250e 92 7 41 22 0 46 8 16 0 xc3s500e 92 7 41 22 0 46 8 16 0 xc3s100e tq144 108 28 40 22 19 42 9 16 0 xc3s250e 108 28 40 20 21 42 9 16 0 xc3s250e pq208 158 32 65 58 25 46 13 16 0 xc3s500e 158 32 65 58 25 46 13 16 0 xc3s250e ft256 172 40 68 62 33 46 15 16 16 xc3s500e 190 41 77 76 33 46 19 16 0 xc3s1200e 190 40 77 78 31 46 19 16 0 xc3s500e fg320 232 56 92 102 48 46 20 16 18 xc3s1200e 250 56 99 120 47 46 21 16 0 xc3s1600e 250 56 99 120 47 46 21 16 0 xc3s1200e fg400 304 72 124 156 62 46 24 16 0 xc3s1600e 304 72 124 156 62 46 24 16 0 xc3s1600e fg484 376 82 156 214 72 46 28 16 0 notes: 1. some vref pins are on input pins. see pinout tables for details. 2. all devices have 24 possible global clock and right- and left-half side clock inputs. the right-half and bottom-edge clock pi ns have shared functionality in some fpga configuration modes. consequently, some clock pins are counted in the dual column. 4 gclk pins, incl uding 2 dual pins, are on input pins. pinout descriptions 168 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r package thermal characteristics the power dissipated by an fpga application has implica- tions on package selection and system design. the power consumed by a spartan-3e fpga is reported using either the xpower estimator or the xpowe r analyze r calculator integrated in the xilinx is e? development software. table 130 provides the thermal characteristics for the vari- ous spartan-3e package offerings. the junction-to-case thermal resistance ( jc ) indicates the difference between the temperature measured on the pack- age body (case) and the die junction temperature per watt of power consumption. the junction-to-board ( jb ) value similarly reports the difference between the board and junc- tion temperature. the junction-to-ambient ( ja ) value reports the temperature difference per watt between the ambient environment and the junction temperature. the ja value is reported at different air velocities, measured in lin- ear feet per minute (lfm). the ?still air (0 lfm)? column shows the ja value in a system without a fan. the thermal resistance drops with increasing air flow. table 130: spartan-3e package thermal characteristics package device junction-to-case ( jc ) junction-to- board ( jb ) junction-to-ambient ( ja ) at different air flows units still air (0 lfm) 250 lfm 500 lfm 750 lfm vq100 xc3s100e 13.0 30.9 49.0 40.7 37.9 37.0 c/watt xc3s250e 11.0 25.9 43.3 36.0 33.6 32.7 c/watt xc3s500e 9.8 40.0 33.3 31.0 30.2 c/watt cp132 xc3s100e 19.3 42.0 62.1 55.3 52.8 51.2 c/watt xc3s250e 11.8 28.1 48.3 41.8 39.5 38.0 c/watt xc3s500e 8.5 21.3 41.5 35.2 32.9 31.5 c/watt tq144 xc3s100e 8.2 31.9 52.1 40.5 34.6 32.5 c/watt xc3s250e 7.2 25.7 37.6 29.2 25.0 23.4 c/watt pq208 xc3s250e 9.8 29.0 37.0 27.3 24.1 22.4 c/watt xc3s500e 8.5 26.8 36.1 26.6 23.6 21.8 c/watt ft256 xc3s250e 12.4 27.7 35.8 29.3 28.4 28.1 c/watt xc3s500e 9.6 22.2 31.1 25.0 24.0 23.6 c/watt xc3s1200e 6.5 16.4 26.2 20.5 19.3 18.9 c/watt fg320 xc3s500e 9.8 15.6 26.1 20.6 19.4 18.6 c/watt xc3s1200e 8.2 12.5 23.0 17.7 16.4 15.7 c/watt xc3s1600e 7.1 10.6 21.1 15.9 14.6 13.8 c/watt fg400 xc3s1200e 7.5 12.4 22.3 17.2 16.0 15.3 c/watt xc3s1600e 6.0 10.4 20.3 15.2 14.0 13.3 c/watt fg484 xc3s1600e 5.7 9.4 18.8 12.5 11.3 10.8 c/watt pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 169 product specification r vq100: 100-lead very-thin quad flat package the xc3s100e, xc3s250e, and the xc3s500e devices are available in the 100-lead very-thin quad flat package, vq100. all devices share a common footprint for this pack- age as shown in ta bl e 1 3 1 and figure 81 . table 131 lists all the package pins. they are sorted by bank number and then by pin name. pins that form a differ- ential i/o pair appear together in the table. the table also shows the pin number for each pin and the pin type, as defined earlier. the vq100 package does not support the byte-wide peripheral interface (bpi) configuration mode. conse- quently, the vq100 footprint has fewer dual-type pins than other packages. an electronic version of this package pinout table and foot- print diagram is available for download from the xilinx web site at: http://www.xilinx.com/support/doc umentation/data_sheets/s3e_pin.zip pinout table table 131 shows the pinout for production spartan-3e fpgas in the vq100 package. table 131: vq100 package pinout bank xc3s100e xc3s250e xc3s500e pin name vq100 pin number type 0 io p92 i/o 0 io_l01n_0 p79 i/o 0 io_l01p_0 p78 i/o 0 io_l02n_0/gclk5 p84 gclk 0 io_l02p_0/gclk4 p83 gclk 0 io_l03n_0/gclk7 p86 gclk 0 io_l03p_0/gclk6 p85 gclk 0 io_l05n_0/gclk11 p91 gclk 0 io_l05p_0/gclk10 p90 gclk 0 io_l06n_0/vref_0 p95 vref 0 io_l06p_0 p94 i/o 0 io_l07n_0/hswap p99 dual 0 io_l07p_0 p98 i/o 0 ip_l04n_0/gclk9 p89 gclk 0 ip_l04p_0/gclk8 p88 gclk 0 vcco_0 p82 vcco 0 vcco_0 p97 vcco 1 io_l01n_1 p54 i/o 1 io_l01p_1 p53 i/o 1 io_l02n_1 p58 i/o 1 io_l02p_1 p57 i/o 1 io_l03n_1/rhclk1 p61 rhclk 1 io_l03p_1/rhclk0 p60 rhclk 1 io_l04n_1/rhclk3 p63 rhclk 1 io_l04p_1/rhclk2 p62 rhclk 1 io_l05n_1/rhclk5 p66 rhclk 1 io_l05p_1/rhclk4 p65 rhclk 1 io_l06n_1/rhclk7 p68 rhclk 1 io_l06p_1/rhclk6 p67 rhclk 1 io_l07n_1 p71 i/o 1 io_l07p_1 p70 i/o 1 ip/vref_1 p69 vref 1 vcco_1 p55 vcco 1 vcco_1 p73 vcco 2 io/d5 p34 dual 2 io/m1 p42 dual 2 io_l01n_2/init_b p25 dual 2 io_l01p_2/cso_b p24 dual 2 io_l02n_2/mosi/csi_b p27 dual 2 io_l02p_2/dout/busy p26 dual 2 io_l03n_2/d6/gclk13 p33 dual/gclk 2 io_l03p_2/d7/gclk12 p32 dual/gclk 2 io_l04n_2/d3/gclk15 p36 dual/gclk 2 io_l04p_2/d4/gclk14 p35 dual/gclk 2 io_l06n_2/d1/gclk3 p41 dual/gclk 2 io_l06p_2/d2/gclk2 p40 dual/gclk 2 io_l07n_2/din/d0 p44 dual 2 io_l07p_2/m0 p43 dual 2 io_l08n_2/vs1 p48 dual 2 io_l08p_2/vs2 p47 dual 2 io_l09n_2/cclk p50 dual 2 io_l09p_2/vs0 p49 dual 2 ip/vref_2 p30 vref 2 ip_l05n_2/m2/gclk1 p39 dual/gclk 2 ip_l05p_2/rdwr_b/ gclk0 p38 dual/gclk 2 vcco_2 p31 vcco 2 vcco_2 p45 vcco 3 io_l01n_3 p3 i/o 3 io_l01p_3 p2 i/o table 131: vq100 package pinout (continued) bank xc3s100e xc3s250e xc3s500e pin name vq100 pin number type pinout descriptions 170 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r 3 io_l02n_3/vref_3 p5 vref 3 io_l02p_3 p4 i/o 3 io_l03n_3/lhclk1 p10 lhclk 3 io_l03p_3/lhclk0 p9 lhclk 3 io_l04n_3/lhclk3 p12 lhclk 3 io_l04p_3/lhclk2 p11 lhclk 3 io_l05n_3/lhclk5 p16 lhclk 3 io_l05p_3/lhclk4 p15 lhclk 3 io_l06n_3/lhclk7 p18 lhclk 3 io_l06p_3/lhclk6 p17 lhclk 3 io_l07n_3 p23 i/o 3 io_l07p_3 p22 i/o 3 ip p13 input 3 vcco_3 p8 vcco 3 vcco_3 p20 vcco gnd gnd p7 gnd gnd gnd p14 gnd gnd gnd p19 gnd gnd gnd p29 gnd gnd gnd p37 gnd gnd gnd p52 gnd gnd gnd p59 gnd gnd gnd p64 gnd gnd gnd p72 gnd gnd gnd p81 gnd gnd gnd p87 gnd gnd gnd p93 gnd vccaux done p51 config vccaux prog_b p1 config vccaux tck p77 jtag vccaux tdi p100 jtag vccaux tdo p76 jtag vccaux tms p75 jtag vccaux vccaux p21 vccaux vccaux vccaux p46 vccaux vccaux vccaux p74 vccaux vccaux vccaux p96 vccaux vccint vccint p6 vccint vccint vccint p28 vccint table 131: vq100 package pinout (continued) bank xc3s100e xc3s250e xc3s500e pin name vq100 pin number type vccint vccint p56 vccint vccint vccint p80 vccint table 131: vq100 package pinout (continued) bank xc3s100e xc3s250e xc3s500e pin name vq100 pin number type pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 171 product specification r user i/os by bank table 132 indicates how the 66 available user-i/o pins are distributed between the four i/o banks on the vq100 pack- age. footprint migration differences the production xc3s100e, xc3s250e, and xc3s500e fpgas have identical footprints in the vq100 package. designs can migrate between the devices without further consideration. table 132: user i/os per bank for xc3s100e, xc3s250e, and xc3s500e in the vq100 package package edge i/o bank maximum i/o all possible i/o pins by type i/o input dual vref (1) clk (1) to p 0 15 5 0 1 1 8 right 1 15 6 0 0 1 8 bottom 2 19 0 0 18 1 0 (2) left 3 17 5 1 2 1 8 total 66 16 1 21 4 24 notes: 1. some vref and clk pins are on input pins. 2. the eight global clock pins in this bank have optional functionality during configuration and are counted in the dual column. pinout descriptions 172 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r vq100 footprint in figure 81 , note pin 1 indicator in top-left corner and logo orientation. figure 81: vq100 package footprint (top view) tdi io_l07 n _0/hs w ap io_l07p_0 v cco_0 v ccaux io_l06 n _0/ v ref_0 io_l06p_0 g n d io io_l05 n _0/gclk11 io_l05p_0/gclk10 ip_l04 n _0/gclk9 ip_l04p_0/gclk 8 g n d io_l03 n _0/gclk7 io_l03p_0/gclk6 io_l02 n _0/gclk5 io_l02p_0/gclk4 v cco_0 g n d v cci n t io_l01 n _0 io_l01p_0 tck tdo 100 99 9 8 97 96 95 94 93 92 91 90 8 9 88 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 79 7 8 77 76 prog_b 1 75 t ms i o _l01p_3 2 74 v cc au x io_l01 n _3 3 73 v cco_1 io_l02p_3 4 72 g n d io_l02 n _3/ v ref_3 5 71 io_l07 n _1 v cci n t 6 70 io_l07p_1 g n d 7 69 ip/ v ref_1 v cco_3 8 6 8 io_l06 n _1/rhclk7 io_l03p_3/lhclk0 9 67 io_l06p_1/rhclk6 io_l03 n _3/lhclk1 10 66 io_l05 n _1/rhclk5 io_l04p_3/lhclk2 11 65 io_l05p_1/rhclk4 io_l04 n _3/lhclk3 12 64 g n d ip 13 63 io_l04 n _1/rhclk3 g n d 14 62 io_l04p_1/rhclk2 io_l05p_3/lhclk4 15 61 io_l03 n _1/rhclk1 io_l05 n _3/lhclk5 16 60 io_l03p_1/rhclk0 io_l06p_3/lhclk6 17 59 g n d io_l06 n _3/lhclk7 1 8 5 8 io_l02 n _1 g n d 19 57 io_l02p_1 v cco_3 20 56 v cci n t v ccaux 21 55 v cco_1 io_l07p_3 22 54 io_l01 n _1 io_l07 n _3 23 53 io_l01p_1 io_l01p_2/cso_b 24 52 g n d io_l01 n _2/i n it_b 25 51 do n e 26 27 2 8 29 30 31 34 37 42 43 44 45 46 47 4 8 49 50 io_l02p_2/dout/busy io_l02 n _2/mosi/csi_b v cci n t g n d ip/ v ref_2 v cco_2 io_l03p_2/d7/gclk12 io_l03 n _2/d6/gclk13 io/d5 io_l04p_2/d4/gclk14 io_l04 n _2/d3/gclk15 g n d ip_l05p_2/rd w r_b/gclk0 ip_l05 n _2/m2/gclk1 io_l06p_2/d2/gclk2 io_l06 n _2/d1/gclk3 io/m1 io_l07p_2/m0 io_l07 n _2/di n /d0 v cco_2 v ccaux io_l0 8 p_2/ v s2 io_l0 8n _2/ v s1 io_l09p_2/ v s0 io_l09 n _2/cclk bank 0 bank 3 bank 2 bank 1 32 33 35 36 3 8 39 40 41 DS312-4_02_0 8 2009 16 i/o: unrestricted, general-purpose user i/o 21 dual: configuration pin, then possible user-i/o 4 vref: user i/o or input voltage reference for bank 1 input: unrestricted, general-purpose input pin 24 clk: user i/o, input, or global buffer input 8 vcco: output voltage supply for bank 2 config: dedicated configuration pins 4 jtag: dedicated jtag port pins 4 vccint: internal core supply voltage (+1.2v) 0 n.c.: not connected 12 gnd: ground 4 vccaux: auxiliary supply voltage (+2.5v) pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 173 product specification r cp132: 132-ball chip-scale package the xc3s100e, xc3s250e and the xc3s500e fpgas are available in the 132-ball chip-scale package, cp132. the devices share a common footprint for this package as shown in ta b l e 1 3 3 and figure 82 . table 133 lists all the cp132 package pins. they are sorted by bank number and then by pin name. pins that form a dif- ferential i/o pair appear together in the table. the table also shows the pin number for each pin and the pin type, as defined earlier. physically, the d14 and k2 balls on the xc3s100e and xc3s250e fpgas are not connected but should be con- nected to vccint to maintain density migration compatibil- ity. similarly, the a4, c1, and p10 balls on the xc3s100e fpga are not connected but should be connected to gnd to maintain density migration compatibility. the xc3s100e fpga has four fewer bpi address pins, a[19:0], whereas the xc3s250e and xc3s500e support a[23:0]. an electronic version of this package pinout table and foot- print diagram is available for download from the xilinx web site at: http://www.xilinx.com/support/doc umentation/data_sheets/s3e_pin.zip pinout table table 133: cp132 package pinout bank xc3s100e pin name xc3s250e xc3s500e pin name cp132 ball type 0 io_l01n_0 io_l01n_0 c12 i/o 0 io_l01p_0 io_l01p_0 a13 i/o 0 n.c. ( ) io_l02n_0 a12 100e: n.c. others: i/o 0 n.c. ( ) io_l02p_0 b12 100e: n.c. others: i/o 0 n.c. ( ) io_l03n_0/vref_0 b11 100e: n.c. others: vref (i/o) 0 ip io_l03p_0 c11 100e: input others: i/o 0 io_l04n_0/gclk5 io_l04n_0/gclk5 c9 gclk 0 io_l04p_0/gclk4 io_l04p_0/gclk4 a10 gclk 0 io_l05n_0/gclk7 io_l05n_0/gclk7 a9 gclk 0 io_l05p_0/gclk6 io_l05p_0/gclk6 b9 gclk 0 io_l07n_0/gclk11 io_l07n_0/gclk11 b7 gclk 0 io_l07p_0/gclk10 io_l07p_0/gclk10 a7 gclk 0 io_l08n_0/vref_0 io_l08n_0/vref_0 c6 vref 0 io_l08p_0 io_l08p_0 b6 i/o 0 io_l09n_0 io_l09n_0 c5 i/o 0 io_l09p_0 io_l09p_0 b5 i/o 0 n.c. ( ) io_l10n_0 c4 100e: n.c. others: i/o 0 ip io_l10p_0 b4 100e: input others: i/o 0 io_l11n_0/hswap io_l11n_0/hswap b3 dual 0 io_l11p_0 io_l11p_0 a3 i/o 0 ip_l06n_0/gclk9 ip_l06n_0/gclk9 c8 gclk 0 ip_l06p_0/gclk8 ip_l06p_0/gclk8 b8 gclk pinout descriptions 174 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r 0 vcco_0 vcco_0 a6 vcco 0 vcco_0 vcco_0 b10 vcco 1 io/a0 io/a0 f12 dual 1 io/vref_1 io/vref_1 k13 vref 1 io_l01n_1/a15 io_l01n_1/a15 n14 dual 1 io_l01p_1/a16 io_l01p_1/a16 n13 dual 1 io_l02n_1/a13 io_l02n_1/a13 m13 dual 1 io_l02p_1/a14 io_l02p_1/a14 m12 dual 1 io_l03n_1/a11 io_l03n_1/a11 l14 dual 1 io_l03p_1/a12 io_l03p_1/a12 l13 dual 1 io_l04n_1/a9/rhclk1 io_l04n_1/a9/rhclk1 j12 rhclk/dual 1 io_l04p_1/a10/rhclk0 io_l04p _1/a10/rhclk0 k14 rhclk/dual 1 io_l05n_1/a7/rhclk3/trdy1 io_l05n_1/a7/rhclk3/trdy1 j14 rhclk/dual 1 io_l05p_1/a8/rhclk2 io_l05p _1/a8/rhclk2 j13 rhclk/dual 1 io_l06n_1/a5/rhclk5 io_l06n_1/a5/rhclk5 h12 rhclk/dual 1 io_l06p_1/a6/rhclk4/irdy1 io_l06p _1/a6/rhclk4/irdy1 h13 rhclk/dual 1 io_l07n_1/a3/rhclk7 io_l07n_1/a3/rhclk7 g13 rhclk/dual 1 io_l07p_1/a4/rhclk6 io_l07p _1/a4/rhclk6 g14 rhclk/dual 1 io_l08n_1/a1 io_l08n_1/a1 f13 dual 1 io_l08p_1/a2 io_l08p_1/a2 f14 dual 1 io_l09n_1/ldc0 io_l09n_1/ldc0 d12 dual 1 io_l09p_1/hdc io_l09p_1/hdc d13 dual 1 io_l10n_1/ldc2 io_l10n_1/ldc2 c13 dual 1 io_l10p_1/ldc1 io_l10p_1/ldc1 c14 dual 1 ip/vref_1 ip/vref_1 g12 vref 1 vcco_1 vcco_1 e13 vcco 1 vcco_1 vcco_1 m14 vcco 2 io/d5 io/d5 p4 dual 2 io/m1 io/m1 n7 dual 2 ip/vref_2 io/vref_2 p11 100e: vref(input) others: vref(i/o) 2 io_l01n_2/init_b io _l01n_2/init_b n1 dual 2 io_l01p_2/cso_b io_l01p_2/cso_b m2 dual 2 io_l02n_2/mosi/csi_b io _l02n_2/mosi/csi_b n2 dual 2 io_l02p_2/dout/busy io_l02p_2/dout/busy p1 dual 2 io_l03n_2/d6/gclk13 io_l03n_2/d6/gclk13 n4 dual/gclk 2 io_l03p_2/d7/gclk12 io_l03p_2/d7/gclk12 m4 dual/gclk 2 io_l04n_2/d3/gclk15 io_l04n_2/d3/gclk15 n5 dual/gclk 2 io_l04p_2/d4/gclk14 io_l04p_2/d4/gclk14 m5 dual/gclk 2 io_l06n_2/d1/gclk3 io_l06n_2/d1/gclk3 p7 dual/gclk table 133: cp132 package pinout (continued) bank xc3s100e pin name xc3s250e xc3s500e pin name cp132 ball type pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 175 product specification r 2 io_l06p_2/d2/gclk2 io_l06p_2/d2/gclk2 p6 dual/gclk 2 io_l07n_2/din/d0 io_l07n_2/din/d0 n8 dual 2 io_l07p_2/m0 io_l07p_2/m0 p8 dual 2 n.c. ( ) io_l08n_2/a22 m9 100e: n.c. others: dual 2 n.c. ( ) io_l08p_2/a23 n9 100e: n.c. others: dual 2 n.c. ( ) io_l09n_2/a20 m10 100e: n.c. others: dual 2 n.c. ( ) io_l09p_2/a21 n10 100e: n.c. others: dual 2 io_l10n_2/vs1/a18 io_l10n_2/vs1/a18 m11 dual 2 io_l10p_2/vs2/a19 io_l10p_2/vs2/a19 n11 dual 2 io_l11n_2/cclk io_l11n_2/cclk n12 dual 2 io_l11p_2/vs0/a17 io_l11p_2/vs0/a17 p12 dual 2 ip/vref_2 ip/vref_2 n3 vref 2 ip_l05n_2/m2/gclk1 ip_l05n _2/m2/gclk1 n6 dual/gclk 2 ip_l05p_2/rdwr_b/gclk0 ip_l05p_2/rdwr_b/gclk0 m6 dual/gclk 2 vcco_2 vcco_2 m8 vcco 2 vcco_2 vcco_2 p3 vcco 3io io j3 i/o 3 ip/vref_3 io/vref_3 k3 100e: vref(input) others: vref(i/o) 3 io_l01n_3 io_l01n_3 b1 i/o 3 io_l01p_3 io_l01p_3 b2 i/o 3 io_l02n_3 io_l02n_3 c2 i/o 3 io_l02p_3 io_l02p_3 c3 i/o 3 n.c. ( ) io_l03n_3 d1 100e: n.c. others: i/o 3 io io_l03p_3 d2 i/o 3 io_l04n_3/lhclk1 io_l04n_3/lhclk1 f2 lhclk 3 io_l04p_3/lhclk0 io_l04p_3/lhclk0 f3 lhclk 3 io_l05n_3/lhclk3/irdy2 io_l05n_3/lhclk3/irdy2 g1 lhclk 3 io_l05p_3/lhclk2 io_l05p_3/lhclk2 f1 lhclk 3 io_l06n_3/lhclk5 io_l06n_3/lhclk5 h1 lhclk 3 io_l06p_3/lhclk4/trdy2 io _l06p_3/lhclk4/trdy2 g3 lhclk 3 io_l07n_3/lhclk7 io_l07n_3/lhclk7 h3 lhclk 3 io_l07p_3/lhclk6 io_l07p_3/lhclk6 h2 lhclk 3 io_l08n_3 io_l08n_3 l2 i/o 3 io_l08p_3 io_l08p_3 l1 i/o 3 io_l09n_3 io_l09n_3 m1 i/o table 133: cp132 package pinout (continued) bank xc3s100e pin name xc3s250e xc3s500e pin name cp132 ball type pinout descriptions 176 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r 3 io_l09p_3 io_l09p_3 l3 i/o 3 ip/vref_3 ip/vref_3 e2 vref 3 vcco_3 vcco_3 e1 vcco 3 vcco_3 vcco_3 j2 vcco gnd n.c. (gnd) gnd a4 gnd gnd gnd gnd a8 gnd gnd n.c. (gnd) gnd c1 gnd gnd gnd gnd c7 gnd gnd gnd gnd c10 gnd gnd gnd gnd e3 gnd gnd gnd gnd e14 gnd gnd gnd gnd g2 gnd gnd gnd gnd h14 gnd gnd gnd gnd j1 gnd gnd gnd gnd k12 gnd gnd gnd gnd m3 gnd gnd gnd gnd m7 gnd gnd gnd gnd p5 gnd gnd n.c. (gnd) gnd p10 gnd gnd gnd gnd p14 gnd vccaux done done p13 config vccaux prog_b prog_b a1 config vccaux tck tck b13 jtag vccaux tdi tdi a2 jtag vccaux tdo tdo a14 jtag vccaux tms tms b14 jtag vccaux vccaux vccaux a5 vccaux vccaux vccaux vccaux e12 vccaux vccaux vccaux vccaux k1 vccaux vccaux vccaux vccaux p9 vccaux vccint vccint vccint a11 vccint vccint vccint vccint d3 vccint vccint n.c. (vccint) vccint d14 vccint vccint n.c. (vccint) vccint k2 vccint vccint vccint vccint l12 vccint vccint vccint vccint p2 vccint table 133: cp132 package pinout (continued) bank xc3s100e pin name xc3s250e xc3s500e pin name cp132 ball type pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 177 product specification r user i/os by bank table 134 shows how the 83 available user-i/o pins are dis- tributed on the xc3s100e fpga packaged in the cp132 package. ta bl e 1 3 5 indicates how the 92 available user-i/o pins are distributed on the xc3s250e and the xc3s500e fpgas in the cp132 package. table 134: user i/os per bank for the xc3s100e in the cp132 package package edge i/o bank maximum i/o all possible i/o pins by type i/o input dual vref (1) clk (1) to p 0 18 6 2 1 1 8 right 1 23 0 0 21 2 0 (2) bottom 2 22 0 0 20 2 0 (2) left 3 20 10 0 0 2 8 total 83 16 2 42 7 16 notes: 1. some vref and clk pins are on input pins. 2. the eight global clock pins in this bank have optional functionality during configuration and are counted in the dual column. table 135: user i/os per bank for the xc3s250e and xc3s500e in the cp132 package package edge i/o bank maximum i/o all possible i/o pins by type i/o input dual vref (1) clk (1) to p 0 22 11 0 1 2 8 right 1 23 0 0 21 2 0 (2) bottom 2 26 0 0 24 2 0 (2) left 3 21 11 0 0 2 8 total 92 22 0 46 8 16 notes: 1. some vref and clk pins are on input pins. 2. the eight global clock pins in this bank have optional functionality during configuration and are counted in the dual column. pinout descriptions 178 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r footprint migration differences table 136 summarizes any footprint and functionality differ- ences between the xc3s100e, the xc3s250e, and the xc3s500e fpgas that may affect easy migration between devices in the cp132 package. there are 14 such balls. all other pins not listed in ta bl e 1 3 6 unconditionally migrate between spartan-3e devices available in the cp132 pack- age. the xc3s100e is duplicated on both the left and right sides of the table to show migrations to and from the xc3s250e and the xc3s500e. the arrows indicate the direction for easy migration. a double-ended arrow ( ) indicates that the two pins have identical functionality. a left-facing arrow ( ) indicates that the pin on the device on the right uncon- ditionally migrates to the pin on the device on the left. it may be possible to migrate the opposite direction depending on the i/o configuration. for example, an i/o pin (type = i/o) can migrate to an input-only pin (type = input) if the i/o pin is configured as an input. the xc3s100e fpga in the cp132 package has four fewer bpi-mode address lines than the xc3s250e and xc3s500e. table 136: cp132 footprint migration differences cp132 ball bank xc3s100e type migration xc3s250e type migration xc3s500e type migration xc3s100e type a12 0 n.c. i/o i/o n.c. b4 0 input i/o i/o input b11 0 n.c. i/o i/o n.c. b12 0 n.c. i/o i/o n.c. c4 0 n.c. i/o i/o n.c. c11 0 input i/o i/o input d1 3 n.c. i/o i/o n.c. d2 3 i/o i/o (diff) i/o (diff) i/o k3 3 vref(input) vref(i/o) vref(i/o) vref(input) m9 2 n.c. dual dual n.c. m10 2 n.c. dual dual n.c. n9 2 n.c. dual dual n.c. n10 2 n.c. dual dual n.c. p11 2 vref(input) vref(i/o) vref(i/o) vref(input) differences 14 0 14 legend: this pin is identical on the device on the left and the right. this pin can unconditionally migrate from the device on the left to the device on the right. migration in the other direction m ay be possible depending on how the pin is configured for the device on the right. this pin can unconditionally migrate from the device on the right to the device on the left. migration in the other direction m ay be possible depending on how the pin is configured for the device on the left. pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 179 product specification r cp132 footprint figure 82: cp132 package footprint (top view) 1234567891011121314 a prog_b tdi tdo tm s tck i/o l11p_0 i/o l07p_0 i/o l05n_0 i/o l04p_0 vccint i/o l02n_0 i/o l01p_0 b i/o l01n_3 i/o l01p_3 i/o l11n_0 hswap i/o l10p_0 i/o l09p_0 i/o l08p_0 i/o l07n_0 input input l06p_0 i/o l05p_0 i/o l03n_0 i/o l02p_0 c i/o l02n_3 i/o l02p_3 i/o l10n_0 i/o l09n_0 i/o l08n_0 l06n_0 gclk9 gclk5 gclk6 gclk7 gclk4 gclk10 gclk11 gclk8 i/o l04n_0 i/o l03p_0 i/o l01n_0 i/o l10n_1 i/o l10p_1 d i/o l03n_3 i/o l03p_3 vccint i/o l09n_1 ldc0 ldc1 ldc2 i/o l09p_1 hdc vccint e gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd vccaux vccaux vccaux vccaux f i/o l05p_3 i/o l04n_3 i/o l04p_3 lhclk0 lhclk1 lhclk2 lhclk5 lhclk6 lhclk7 i/o a0 i/o l08n_1 a1 i/o l08p_1 a2 g i/o l05n_3 lhclk3 i/o l06p_3 lhclk4 trdy2 irdy2 vref_1 vref_1 vref_2 vref_2 vref_3 vref_3 vref_0 vref_0 h i/o l06n_3 i/o l07p_3 i/o l07n_3 j i/o i/o i/o k vccint i/o i/o l i/o l08p_3 i/o l08n_3 i/o l09p_3 vccint i/o l03p_1 a12 i/o l03n_1 a11 m i/o l09n_3 i/o l01p_2 cso_b i/o l08n_2 a22 i/o l09n_2 a20 i/o l10n_2 vs1 a18 i/o l02p_1 a14 i/o l02n_1 a13 n i/o l01n_2 init_b i/o l02n_2 mosi csi_b i/o m1 i/o l07n_2 din d0 i/o l08p_2 a23 i/o l09p_2 a21 i/o l10p_2 vs2 a19 i/o l11n_2 cclk i/o l01p_1 a16 i/o l01n_1 a15 p i/o l02p_2 dout busy vccint vcco_2 vcco_2 vcco_1 vcco_1 vcco_0 vcco_0 vcco_3 vcco_3 i/o d5 i/o l07p_2 m0 i/o i/o l11p_2 vs0 a17 done bank 2 bank 0 bank 3 bank 1 i/o l07p_1 4 rhclk6 l07n_1 rhclk7 a 3 i/o rhclk5 a 5 l06n_1 i/o rhclk4 a6 l06p_1 i/o a rhclk3 l05n_1 i/o 7 a rhclk2 a 8 l05p_1 rhclk1 a 9 l04n_1 rhclk0 a 10 l04p_1 i/o i/o l06n_2 d1 gclk3 i/o l06p_2 d2 gclk2 l05n_2 m2 gclk1 input input input input input l05p_2 rdwr_b gclk0 i/o l04n_2 d3 gclk15 i/o l03n_2 d6 gclk13 i/o l04p_2 d4 gclk14 i/o l03p_2 d7 gclk12 irdy1 trdy1 DS312-4_07_030206 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 16 to 22 i/o: unrestricted, general-purpose user i/o 42 to 46 dual: configuration pin, then possible user i/o 7 to 8 vref: user i/o or input voltage reference for bank 0 to 2 input: unrestricted, general-purpose input pin 16 clk: user i/o, input, or global buffer input 8 vcco: output voltage supply for bank 2 config: dedicated configuration pins 4 jtag: dedicated jtag port pins 6 vccint: internal core supply voltage (+1.2v) 9 n.c.: unconnected balls on the xc3s100e fpga ( ) 16 gnd: ground 4 vccaux: auxiliary supply voltage (+2.5v) pinout descriptions 180 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r tq144: 144-lead thin quad flat package the xc3s100e and the xc3s250e fpgas are available in the 144-lead thin quad flat package, tq144. both devices share a common footprint for this package as shown in table 137 and figure 83 . table 137 lists all the package pins. they are sorted by bank number and then by pin name of the largest device. pins that form a differential i/o pair appear together in the table. the table also shows the pin number for each pin and the pin type, as defined earlier. the tq144 package only supports 20 address output pins in the byte-wide peripheral interface (bpi) configuration mode. in larger packages, there are 24 bpi address out- puts. an electronic version of this package pinout table and foot- print diagram is available for download from the xilinx web site at: http://www.xilinx.com/support/doc umentation/data_sheets/s3e_pin.zip pinout table table 137: tq144 package pinout bank xc3s100e pin name xc3s250e pin name tq144 pin type 0 io io p132 i/o 0 io/vref_0 io/vref_0 p124 vref 0 io_l01n_0 io_l01n_0 p113 i/o 0 io_l01p_0 io_l01p_0 p112 i/o 0 io_l02n_0 io_l02n_0 p117 i/o 0 io_l02p_0 io_l02p_0 p116 i/o 0 io_l04n_0/gclk5 io_l04n_0/gclk5 p123 gclk 0 io_l04p_0/gclk4 io_l04p_0/gclk4 p122 gclk 0 io_l05n_0/gclk7 io_l05n_0/gclk7 p126 gclk 0 io_l05p_0/gclk6 io_l05p_0/gclk6 p125 gclk 0 io_l07n_0/gclk11 io_l07n_0/gclk11 p131 gclk 0 io_l07p_0/gclk10 io_l07p_0/gclk10 p130 gclk 0 io_l08n_0/vref_0 io_l08n_0/vref_0 p135 vref 0 io_l08p_0 io_l08p_0 p134 i/o 0 io_l09n_0 io_l09n_0 p140 i/o 0 io_l09p_0 io_l09p_0 p139 i/o 0 io_l10n_0/hswap io_l10n_0/hswap p143 dual 0 io_l10p_0 io_l10p_0 p142 i/o 0 ip ip p111 input 0 ip ip p114 input 0 ip ip p136 input 0 ip ip p141 input 0 ip_l03n_0 ip_l03n_0 p120 input 0 ip_l03p_0 ip_l03p_0 p119 input 0 ip_l06n_0/gclk9 ip_l06n_0/gclk9 p129 gclk 0 ip_l06p_0/gclk8 ip_l06p_0/gclk8 p128 gclk 0 vcco_0 vcco_0 p121 vcco 0 vcco_0 vcco_0 p138 vcco 1 io/a0 io/a0 p98 dual 1 io/vref_1 io/vref_1 p83 vref 1 io_l01n_1/a15 io_l01n_1/a15 p75 dual pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 181 product specification r 1 io_l01p_1/a16 io_l01p_1/a16 p74 dual 1 io_l02n_1/a13 io_l02n_1/a13 p77 dual 1 io_l02p_1/a14 io_l02p_1/a14 p76 dual 1 io_l03n_1/a11 io_l03n_1/a11 p82 dual 1 io_l03p_1/a12 io_l03p_1/a12 p81 dual 1 io_l04n_1/a9/rhclk1 io_l04n_1/a9/rhclk1 p86 rhclk/dual 1 io_l04p_1/a10/rhclk0 io_l04p_1/a10/rhclk0 p85 rhclk/dual 1 io_l05n_1/a7/rhclk3/trdy1 io_l05n_1/a7/rhclk3 p88 rhclk/dual 1 io_l05p_1/a8/rhclk2 io_l05p_1/a8/rhclk2 p87 rhclk/dual 1 io_l06n_1/a5/rhclk5 io_l06n_1/a5/rhclk5 p92 rhclk/dual 1 io_l06p_1/a6/rhclk4/irdy1 io_l06p_1/a6/rhclk4 p91 rhclk/dual 1 io_l07n_1/a3/rhclk7 io_l07n_1/a3/rhclk7 p94 rhclk/dual 1 io_l07p_1/a4/rhclk6 io_l07p_1/a4/rhclk6 p93 rhclk/dual 1 io_l08n_1/a1 io_l08n_1/a1 p97 dual 1 io_l08p_1/a2 io_l08p_1/a2 p96 dual 1 io_l09n_1/ldc0 io_l09n_1/ldc0 p104 dual 1 io_l09p_1/hdc io_l09p_1/hdc p103 dual 1 io_l10n_1/ldc2 io_l10n_1/ldc2 p106 dual 1 io_l10p_1/ldc1 io_l10p_1/ldc1 p105 dual 1 ip ip p78 input 1 ip ip p84 input 1 ip ip p89 input 1 ip ip p101 input 1 ip ip p107 input 1 ip/vref_1 ip/vref_1 p95 vref 1 vcco_1 vcco_1 p79 vcco 1 vcco_1 vcco_1 p100 vcco 2 io/d5 io/d5 p52 dual 2 io/m1 io/m1 p60 dual 2 ip/vref_2 io/vref_2 p66 100e: vref(input) 250e: vref(i/o) 2 io_l01n_2/init_b io_l01n_2/init_b p40 dual 2 io_l01p_2/cso_b io_l01p_2/cso_b p39 dual 2 io_l02n_2/mosi/csi_b io_l02n_2/mosi/csi_b p44 dual 2 io_l02p_2/dout/busy io_l02p_2/dout/busy p43 dual 2 io_l04n_2/d6/gclk13 io_l04n_2/d6/gclk13 p51 dual/gclk 2 io_l04p_2/d7/gclk12 io_l04p_2/d7/gclk12 p50 dual/gclk 2 io_l05n_2/d3/gclk15 io_l05n_2/d3/gclk15 p54 dual/gclk 2 io_l05p_2/d4/gclk14 io_l05p_2/d4/gclk14 p53 dual/gclk 2 io_l07n_2/d1/gclk3 io_l07n_2/d1/gclk3 p59 dual/gclk 2 io_l07p_2/d2/gclk2 io_l07p_2/d2/gclk2 p58 dual/gclk 2 io_l08n_2/din/d0 io_l08n_2/din/d0 p63 dual table 137: tq144 package pinout (continued) bank xc3s100e pin name xc3s250e pin name tq144 pin type pinout descriptions 182 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r 2 io_l08p_2/m0 io_l08p_2/m0 p62 dual 2 io_l09n_2/vs1/a18 io_l09n_2/vs1/a18 p68 dual 2 io_l09p_2/vs2/a19 io_l09p_2/vs2/a19 p67 dual 2 io_l10n_2/cclk io_l10n_2/cclk p71 dual 2 io_l10p_2/vs0/a17 io_l10p_2/vs0/a17 p70 dual 2 ip ip p38 input 2 ip ip p41 input 2 ip ip p69 input 2 ip_l03n_2/vref_2 ip_l03n_2/vref_2 p48 vref 2 ip_l03p_2 ip_l03p_2 p47 input 2 ip_l06n_2/m2/gclk1 ip_l06n_2/m2/gclk1 p57 dual/gclk 2 ip_l06p_2/rdwr_b/gclk0 ip_l06p_2/rdwr_b/gclk0 p56 dual/gclk 2 vcco_2 vcco_2 p42 vcco 2 vcco_2 vcco_2 p49 vcco 2 vcco_2 vcco_2 p64 vcco 3 ip/vref_3 io/vref_3 p31 100e: vref(input) 250e: vref(i/o) 3 io_l01n_3 io_l01n_3 p3 i/o 3 io_l01p_3 io_l01p_3 p2 i/o 3 io_l02n_3/vref_3 io_l02n_3/vref_3 p5 vref 3 io_l02p_3 io_l02p_3 p4 i/o 3 io_l03n_3 io_l03n_3 p8 i/o 3 io_l03p_3 io_l03p_3 p7 i/o 3 io_l04n_3/lhclk1 io_l04n_3/lhclk1 p15 lhclk 3 io_l04p_3/lhclk0 io_l04p_3/lhclk0 p14 lhclk 3 io_l05n_3/lhclk3/irdy2 io_l05n_3/lhclk3 p17 lhclk 3 io_l05p_3/lhclk2 io_l05p_3/lhclk2 p16 lhclk 3 io_l06n_3/lhclk5 io_l06n_3/lhclk5 p21 lhclk 3 io_l06p_3/lhclk4/trdy2 io_l06p_3/lhclk4 p20 lhclk 3 io_l07n_3/lhclk7 io_l07n_3/lhclk7 p23 lhclk 3 io_l07p_3/lhclk6 io_l07p_3/lhclk6 p22 lhclk 3 io_l08n_3 io_l08n_3 p26 i/o 3 io_l08p_3 io_l08p_3 p25 i/o 3 io_l09n_3 io_l09n_3 p33 i/o 3 io_l09p_3 io_l09p_3 p32 i/o 3 io_l10n_3 io_l10n_3 p35 i/o 3 io_l10p_3 io_l10p_3 p34 i/o 3 ip ip p6 input 3 io ip p10 100e: i/o 250e: input 3 ip ip p18 input 3 ip ip p24 input table 137: tq144 package pinout (continued) bank xc3s100e pin name xc3s250e pin name tq144 pin type pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 183 product specification r 3 io ip p29 100e: i/o 250e: input 3 ip ip p36 input 3 ip/vref_3 ip/vref_3 p12 vref 3 vcco_3 vcco_3 p13 vcco 3 vcco_3 vcco_3 p28 vcco gnd gnd gnd p11 gnd gnd gnd gnd p19 gnd gnd gnd gnd p27 gnd gnd gnd gnd p37 gnd gnd gnd gnd p46 gnd gnd gnd gnd p55 gnd gnd gnd gnd p61 gnd gnd gnd gnd p73 gnd gnd gnd gnd p90 gnd gnd gnd gnd p99 gnd gnd gnd gnd p118 gnd gnd gnd gnd p127 gnd gnd gnd gnd p133 gnd vccaux done done p72 config vccaux prog_b prog_b p1 config vccaux tck tck p110 jtag vccaux tdi tdi p144 jtag vccaux tdo tdo p109 jtag vccaux tms tms p108 jtag vccaux vccaux vccaux p30 vccaux vccaux vccaux vccaux p65 vccaux vccaux vccaux vccaux p102 vccaux vccaux vccaux vccaux p137 vccaux vccint vccint vccint p9 vccint vccint vccint vccint p45 vccint vccint vccint vccint p80 vccint vccint vccint vccint p115 vccint table 137: tq144 package pinout (continued) bank xc3s100e pin name xc3s250e pin name tq144 pin type pinout descriptions 184 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r user i/os by bank table 138 and table 139 indicate how the 108 available user-i/o pins are distributed between the four i/o banks on the tq144 package. footprint migration differences table 140 summarizes any footprint and functionality differ- ences between the xc3s100e and the xc3s250e fpgas that may affect easy migration between devices. there are four such pins. all other pins not listed in ta bl e 1 4 0 uncon- ditionally migrate between spartan-3e devices available in the tq144 package. the arrows indicate the direction for easy migration. for example, a left-facing arrow indicates that the pin on the xc3s250e unconditionally migrates to the pin on the xc3s100e. it may be possible to migrate the opposite direction depending on the i/o configuration. for example, an i/o pin (type = i/o) can migrate to an input-only pin (type = input) if the i/o pin is configured as an input. table 138: user i/os per bank for the xc3s100e in the tq144 package package edge i/o bank maximum i/o all possible i/o pins by type i/o input dual vref (1) clk (1) to p 0 26 9 6 1 2 8 right 1 28 0 5 21 2 0 (1) bottom 2 26 0 4 20 2 0 (1) left 3 28 13 4 0 3 8 total 108 22 19 42 9 16 notes: 1. some vref and clk pins are on input pins. 2. the eight global clock pins in this bank have optional functionality during configuration and are counted in the dual column. table 139: user i/os per bank for the xc3s250e in tq144 package package edge i/o bank maximum i/o all possible i/o pins by type i/o input dual vref (1) clk (1) to p 0 26 9 6 1 2 8 right 1 28 0 5 21 2 0 (2) bottom 2 26 0 4 20 2 0 (2) left 3 28 11 6 0 3 8 total 108 20 21 42 9 16 notes: 1. some vref and clk pins are on input pins. 2. the eight global clock pins in this bank have optional functionality during configuration and are counted in the dual column. table 140: tq144 footprint migration differences tq144 pin bank xc3s100e type migration xc3s250e type p10 3 i/o input p29 3 i/o input p31 3 vref(input) vref(i/o) p66 2 vref(input) vref(i/o) differences 4 this pin can unconditionally migrate from the device on the left to the device on the right. migration in the other direction m ay be possible depending on how the pin is configured for the device on the right. this pin can unconditionally migrate from the device on the right to the device on the left. migration in the other direction m ay be possible depending on how the pin is configured for the device on the left. pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 185 product specification r tq144 footprint note pin 1 indicator in top-left corner and logo orientation. double arrows ( ) indicates a pinout migration difference between the xc3s100e and xc3s250e. figure 83: tq144 package footprint (top view) tdi io_l10 n _0/hs w ap io_l10p_0 ip io_l09 n _0 io_l09p_0 v cco_0 v ccaux ip io_l0 8n _0/ v ref_0 io_l0 8 p_0 g n d io io_l07 n _0/gclk11 io_l07p_0/gclk10 ip_l06 n _0/gclk9 ip_l06p_0/gclk 8 g n d io_l05 n _0/gclk7 io_l05p_0/gclk6 io/ v ref_0 io_l04 n _0/gclk5 io_l04p_0/gclk4 v cco_0 ip_l03 n _0 ip_l03p_0 g n d io_l02 n _0 io_l02p_0 v cci n t ip io_l01 n _0 io_l01p_0 ip tck tdo 144 143 142 141 140 139 13 8 137 136 135 134 133 132 131 130 129 12 8 127 126 125 124 123 122 121 120 119 11 8 117 116 115 114 113 112 111 110 109 prog_b 1 10 8 tms io_l01p_3 2 107 ip io_l01 n _3 3 106 io_l10 n _1/ldc2 io_l02p_3 4 105 io_l10p_1/ldc1 io_l02 n _3/ v ref_3 5 104 io_l09 n _1/ldc0 ip 6 103 io_l09p_1/hdc io_l03p_3 7 102 v ccaux io_l03 n _3 8 101 ip v cci n t 9 100 v cco_1 ( )ip 10 99 g n d g n d 11 9 8 io/a0 ip/ v ref_3 12 97 io_l0 8n _1/a1 v cco_3 13 96 io_l0 8 p_1/a2 io_l04p_3/lhclk0 14 95 ip/ v ref_1 io_l04 n _3/lhclk1 15 io_l07 n _1/a3/rhclk7 io_l05p_3/lhclk2 16 io_l07p_1/a4/rhclk6 io_l05 n _3/lhclk3 17 io_l06 n _1/a5/rhclk5 ip 1 8 io_l06p_1/a6/rhclk4 g n d 19 90 g n d io_l06p_3/lhclk4 20 8 9ip io_l06 n _3/lhclk5 21 io_l05 n _1/a7/rhclk3 io_l07p_3/lhclk6 22 io_l05p_1/a 8 /rhclk2 io_l07 n _3/lhclk7 23 io_l04 n _1/a9/rhclk1 ip 24 io_l04p_1/a10/rhclk0 io_l0 8 p_3 25 8 4ip io_l0 8n _3 26 8 3io/ v ref_1 g n d 27 8 2 io_l03 n _1/a11 v cco_3 2 8 8 1 io_l03p_1/a12 ( )ip 29 8 0 v cci n t v ccaux 30 79 v cco_1 ( )io/ v ref_3 31 7 8 ip io_l09p_3 32 77 io_l02 n _1/a13 io_l09 n _3 33 76 io_l02p_1/a14 io_l10p_3 34 75 io_l01 n _1/a15 io_l10 n _3 35 74 io_l01p_1/a16 ip 36 73 g n d 37 3 8 39 40 41 42 43 44 45 46 47 4 8 49 52 55 60 61 62 63 64 65 66 67 6 8 69 70 71 72 g n d ip io_l01p_2/cso_b io_l01 n _2/i n it_b ip v cco_2 io_l02p_2/dout/busy io_l02 n _2/mosi/csi_b v cci n t g n d ip_l03p_2 ip_l03 n _2/ v ref_2 v cco_2 io_l04p_2/d7/gclk12 io_l04 n _2/d6/gclk13 io/d5 io_l05p_2/d4/gclk14 io_l05 n _2/d3/gclk15 g n d ip_l06p_2/rd w r_b/gclk0 ip_l06 n _2/m2/gclk1 io_l07p_2/d2/gclk2 io_l07 n _2/d1/gclk3 io/m1 g n d io_l0 8 p_2/m0 io_l0 8n _2/di n /d0 v cco_2 v ccaux ( )io/ v ref_2 io_l09p_2/ v s2/a19 io_l09 n _2/ v s1/a1 8 ip io_l10p_2/ v s0/a17 io_l10 n _2/cclk do n e bank 0 bank 3 bank 1 bank 2 50 51 53 54 56 57 5 8 59 8 5 8 6 8 7 88 91 92 93 94 DS312-4_01_0 8 2009 20 i/o: unrestricted, general-purpose user i/o 42 dual: configuration pin, then possible user i/o 9 vref: user i/o or input voltage reference for bank 21 input: unrestricted, general-purpose input pin 16 clk: user i/o, input, or global buffer input 9 vcco: output voltage supply for bank 2 config: dedicated configuration pins 4 jtag: dedicated jtag port pins 4 vccint: internal core supply voltage (+1.2v) 0 n.c.: not connected 13 gnd: ground 4 vccaux: auxiliary supply voltage (+2.5v) pinout descriptions 186 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r pq208: 208-pin plastic quad flat package the 208-pin plastic quad flat package, pq208, supports two different spartan-3e fpgas, including the xc3s250e and the xc3s500e. table 141 lists all the pq208 package pins. they are sorted by bank number and then by pin name. pairs of pins that form a differential i/o pair appear together in the table. the table also shows the pin number for each pin and the pin type, as defined earlier. an electronic version of this package pinout table and foot- print diagram is available for download from the xilinx web- site at: http://www.xilinx.com/support/doc umentation/data_sheets/s3e_pin.zip . pinout table table 141: pq208 package pinout bank xc3s250e xc3s500e pin name pq208 pin type 0 io p187 i/o 0 io/vref_0 p179 vref 0 io_l01n_0 p161 i/o 0 io_l01p_0 p160 i/o 0 io_l02n_0/vref_0 p163 vref 0 io_l02p_0 p162 i/o 0 io_l03n_0 p165 i/o 0 io_l03p_0 p164 i/o 0 io_l04n_0/vref_0 p168 vref 0 io_l04p_0 p167 i/o 0 io_l05n_0 p172 i/o 0 io_l05p_0 p171 i/o 0 io_l07n_0/gclk5 p178 gclk 0 io_l07p_0/gclk4 p177 gclk 0 io_l08n_0/gclk7 p181 gclk 0 io_l08p_0/gclk6 p180 gclk 0 io_l10n_0/gclk11 p186 gclk 0 io_l10p_0/gclk10 p185 gclk 0 io_l11n_0 p190 i/o 0 io_l11p_0 p189 i/o 0 io_l12n_0/vref_0 p193 vref 0 io_l12p_0 p192 i/o 0 io_l13n_0 p197 i/o 0 io_l13p_0 p196 i/o 0 io_l14n_0/vref_0 p200 vref 0 io_l14p_0 p199 i/o 0 io_l15n_0 p203 i/o 0 io_l15p_0 p202 i/o 0 io_l16n_0/hswap p206 dual 0 io_l16p_0 p205 i/o 0 ip p159 input 0 ip p169 input 0 ip p194 input 0 ip p204 input 0 ip_l06n_0 p175 input 0 ip_l06p_0 p174 input 0 ip_l09n_0/gclk9 p184 gclk 0 ip_l09p_0/gclk8 p183 gclk 0 vcco_0 p176 vcco 0 vcco_0 p191 vcco 0 vcco_0 p201 vcco 1 io_l01n_1/a15 p107 dual 1 io_l01p_1/a16 p106 dual 1 io_l02n_1/a13 p109 dual 1 io_l02p_1/a14 p108 dual 1 io_l03n_1/vref_1 p113 vref 1 io_l03p_1 p112 i/o 1 io_l04n_1 p116 i/o 1 io_l04p_1 p115 i/o 1 io_l05n_1/a11 p120 dual 1 io_l05p_1/a12 p119 dual 1 io_l06n_1/vref_1 p123 vref 1 io_l06p_1 p122 i/o 1 io_l07n_1/a9/rhclk1 p127 rhclk/dual 1 io_l07p_1/a10/rhclk0 p126 rhclk/dual 1 io_l08n_1/a7/rhclk3 p129 rhclk/dual 1 io_l08p_1/a8/rhclk2 p128 rhclk/dual 1 io_l09n_1/a5/rhclk5 p133 rhclk/dual 1 io_l09p_1/a6/rhclk4 p132 rhclk/dual 1 io_l10n_1/a3/rhclk7 p135 rhclk/dual 1 io_l10p_1/a4/rhclk6 p134 rhclk/dual 1 io_l11n_1/a1 p138 dual 1 io_l11p_1/a2 p137 dual 1 io_l12n_1/a0 p140 dual 1 io_l12p_1 p139 i/o 1 io_l13n_1 p145 i/o table 141: pq208 package pinout (continued) bank xc3s250e xc3s500e pin name pq208 pin type pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 187 product specification r 1 io_l13p_1 p144 i/o 1 io_l14n_1 p147 i/o 1 io_l14p_1 p146 i/o 1 io_l15n_1/ldc0 p151 dual 1 io_l15p_1/hdc p150 dual 1 io_l16n_1/ldc2 p153 dual 1 io_l16p_1/ldc1 p152 dual 1 ip p110 input 1 ip p118 input 1 ip p124 input 1 ip p130 input 1 ip p142 input 1 ip p148 input 1 ip p154 input 1 ip/vref_1 p136 vref 1 vcco_1 p114 vcco 1 vcco_1 p125 vcco 1 vcco_1 p143 vcco 2 io/d5 p76 dual 2 io/m1 p84 dual 2 io/vref_2 p98 vref 2 io_l01n_2/init_b p56 dual 2 io_l01p_2/cso_b p55 dual 2 io_l03n_2/mosi/csi_b p61 dual 2 io_l03p_2/dout/busy p60 dual 2 io_l04n_2 p63 i/o 2 io_l04p_2 p62 i/o 2 io_l05n_2 p65 i/o 2 io_l05p_2 p64 i/o 2 io_l06n_2 p69 i/o 2 io_l06p_2 p68 i/o 2 io_l08n_2/d6/gclk13 p75 dual/gclk 2 io_l08p_2/d7/gclk12 p74 dual/gclk 2 io_l09n_2/d3/gclk15 p78 dual/gclk 2 io_l09p_2/d4/gclk14 p77 dual/gclk 2 io_l11n_2/d1/gclk3 p83 dual/gclk 2 io_l11p_2/d2/gclk2 p82 dual/gclk 2 io_l12n_2/din/d0 p87 dual 2 io_l12p_2/m0 p86 dual 2 io_l13n_2 p90 i/o table 141: pq208 package pinout (continued) bank xc3s250e xc3s500e pin name pq208 pin type 2 io_l13p_2 p89 i/o 2 io_l14n_2/a22 p94 dual 2 io_l14p_2/a23 p93 dual 2 io_l15n_2/a20 p97 dual 2 io_l15p_2/a21 p96 dual 2 io_l16n_2/vs1/a18 p100 dual 2 io_l16p_2/vs2/a19 p99 dual 2 io_l17n_2/cclk p103 dual 2 io_l17p_2/vs0/a17 p102 dual 2 ip p54 input 2 ip p91 input 2 ip p101 input 2 ip_l02n_2 p58 input 2 ip_l02p_2 p57 input 2 ip_l07n_2/vref_2 p72 vref 2 ip_l07p_2 p71 input 2 ip_l10n_2/m2/gclk1 p81 dual/gclk 2 ip_l10p_2/rdwr_b/ gclk0 p80 dual/gclk 2 vcco_2 p59 vcco 2 vcco_2 p73 vcco 2 vcco_2 p88 vcco 3 io/vref_3 p45 vref 3 io_l01n_3 p3 i/o 3 io_l01p_3 p2 i/o 3 io_l02n_3/vref_3 p5 vref 3 io_l02p_3 p4 i/o 3 io_l03n_3 p9 i/o 3 io_l03p_3 p8 i/o 3 io_l04n_3 p12 i/o 3 io_l04p_3 p11 i/o 3 io_l05n_3 p16 i/o 3 io_l05p_3 p15 i/o 3 io_l06n_3 p19 i/o 3 io_l06p_3 p18 i/o 3 io_l07n_3/lhclk1 p23 lhclk 3 io_l07p_3/lhclk0 p22 lhclk 3 io_l08n_3/lhclk3 p25 lhclk 3 io_l08p_3/lhclk2 p24 lhclk 3 io_l09n_3/lhclk5 p29 lhclk 3 io_l09p_3/lhclk4 p28 lhclk table 141: pq208 package pinout (continued) bank xc3s250e xc3s500e pin name pq208 pin type pinout descriptions 188 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r 3 io_l10n_3/lhclk7 p31 lhclk 3 io_l10p_3/lhclk6 p30 lhclk 3 io_l11n_3 p34 i/o 3 io_l11p_3 p33 i/o 3 io_l12n_3 p36 i/o 3 io_l12p_3 p35 i/o 3 io_l13n_3 p40 i/o 3 io_l13p_3 p39 i/o 3 io_l14n_3 p42 i/o 3 io_l14p_3 p41 i/o 3 io_l15n_3 p48 i/o 3 io_l15p_3 p47 i/o 3 io_l16n_3 p50 i/o 3 io_l16p_3 p49 i/o 3 ip p6 input 3 ip p14 input 3 ip p26 input 3 ip p32 input 3 ip p43 input 3 ip p51 input 3 ip/vref_3 p20 vref 3 vcco_3 p21 vcco 3 vcco_3 p38 vcco 3 vcco_3 p46 vcco gnd gnd p10 gnd gnd gnd p17 gnd gnd gnd p27 gnd gnd gnd p37 gnd gnd gnd p52 gnd gnd gnd p53 gnd gnd gnd p70 gnd gnd gnd p79 gnd gnd gnd p85 gnd gnd gnd p95 gnd gnd gnd p105 gnd gnd gnd p121 gnd gnd gnd p131 gnd gnd gnd p141 gnd gnd gnd p156 gnd gnd gnd p173 gnd table 141: pq208 package pinout (continued) bank xc3s250e xc3s500e pin name pq208 pin type gnd gnd p182 gnd gnd gnd p188 gnd gnd gnd p198 gnd gnd gnd p208 gnd vccaux done p104 config vccaux prog_b p1 config vccaux tck p158 jtag vccaux tdi p207 jtag vccaux tdo p157 jtag vccaux tms p155 jtag vccaux vccaux p7 vccaux vccaux vccaux p44 vccaux vccaux vccaux p66 vccaux vccaux vccaux p92 vccaux vccaux vccaux p111 vccaux vccaux vccaux p149 vccaux vccaux vccaux p166 vccaux vccaux vccaux p195 vccaux vccint vccint p13 vccint vccint vccint p67 vccint vccint vccint p117 vccint vccint vccint p170 vccint table 141: pq208 package pinout (continued) bank xc3s250e xc3s500e pin name pq208 pin type pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 189 product specification r user i/os by bank table 142 indicates how the 158 available user-i/o pins are distributed between the four i/o banks on the pq208 pack- age. footprint migrat ion differences the xc3s250e and xc3s500e fpgas have identical foot- prints in the pq208 package. designs can migrate between the xc3s250e and xc3s500e without further consider- ation. table 142: user i/os per bank for the xc3s250e and xc3s500e in the pq208 package package edge i/o bank maximum i/o all possible i/o pins by type i/o input dual vref (1) clk (1) to p 0 38 18 6 1 5 8 right 1 40 9 7 21 3 0 (2) bottom 2 40 8 6 24 2 0 (2) left 3 40 23 6 0 3 8 total 158 58 25 46 13 16 notes: 1. some vref and clk pins are on input pins. 2. the eight global clock pins in this bank have optional functionality during configuration and are counted in the dual column. pinout descriptions 190 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r pq208 footprint (left) figure 84: pq208 footprint (left) g n d tdi io_l16 n _0/hs w ap io_l16p_0 ip io_l15 n _0 io_l15p_0 v cco_0 io_l14 n _0/ v ref_0 io_l14p_0 g n d io_l13 n _0 io_l13p_0 v ccaux ip io_l12 n _0/ v ref_0 io_l12p_0 v cco_0 io_l11 n _0 io_l11p_0 g n d io io_l10 n _0/gclk11 io_l10p_0/gclk10 ip_l09 n _0/gclk9 ip_l09p_0/gclk 8 g n d 20 8 207 206 205 204 203 202 201 200 199 19 8 197 196 195 194 193 192 191 190 1 8 9 1 88 1 8 7 1 8 6 1 8 5 1 8 4 1 8 3 1 8 2 prog_b 1 io _ l 01 p _3 2 io_l01 n _3 3 io_l02p_3 4 io_l02 n _3/ v ref_3 5 ip 6 v ccaux 7 io_l03p_3 8 io_l03 n _3 9 g n d 10 io_l04p_3 11 io_l04 n _3 12 v cci n t 13 ip 14 io_l05p_3 15 io_l05 n _3 16 g n d 17 io_l06p_3 1 8 io_l06 n _3 19 ip/ v ref_3 20 v cco_3 21 io_l07p_3/lhclk0 22 io_l07 n _3/lhclk1 23 io_l0 8 p_3/lhclk2 24 io_l0 8n _3/lhclk3 25 ip 26 g n d 27 io_l09p_3/lhclk4 2 8 io_l09 n _3/lhclk5 29 io_l10p_3/lhclk6 30 io_l10 n _3/lhclk7 31 ip 32 io_l11p_3 33 io_l11 n _3 34 io_l12p_3 35 io_l12 n _3 36 g n d 37 v cco_3 3 8 io_l13p_3 39 io_l13 n _3 40 io_l14p_3 41 io_l14 n _3 42 ip 43 v ccaux 44 io/ v ref_3 45 v cco_3 46 io_l15p_3 47 io_l15 n _3 4 8 io_l16p_3 49 io_l16 n _3 50 ip 51 g n d 52 53 54 55 56 57 5 8 59 60 61 62 63 64 65 66 67 6 8 69 70 71 72 73 76 79 g n d ip io_l01p_2/cso_b io_l01 n _2/i n it_b ip_l02p_2 ip_l02 n _2 v cco_2 io_l03p_2/dout/busy io_l03 n _2/mosi/csi_b io_l04p_2 io_l04 n _2 io_l05p_2 io_l05 n _2 v ccaux v cci n t io_l06p_2 io_l06 n _2 g n d ip_l07p_2 ip_l07 n _2/ v ref_2 v cco_2 io_l0 8 p_2/d7/gclk12 io_l0 8n _2/d6/gclk13 io/d5 io_l09p_2/d4/gclk14 io_l09 n _2/d3/gclk15 g n d bank 0 bank 3 bank 2 74 75 77 7 8 DS312-4_03_030705 pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 191 product specification r pq208 footprint (right) figure 85: pq208 footprint (right) io_l0 8n _0/gclk7 io_l0 8 p_0/gclk6 io/ v ref_0 io_l07 n _0/gclk5 io_l07p_0/gclk4 v cco_0 ip_l06 n _0 ip_l06p_0 g n d io_l05 n _0 io_l05p_0 v cci n t ip io_l04 n _0/ v ref_0 io_l04p_0 v ccaux io_l03 n _0 io_l03p_0 io_l02 n _0/ v ref_0 io_l02p_0 io_l01 n _0 io_l01p_0 ip tck tdo 1 8 1 1 8 0 179 17 8 177 176 175 174 173 172 171 170 169 16 8 167 166 165 164 163 162 161 160 159 15 8 157 156 g n d 155 tms 154 ip 153 io_l16 n _1/ldc2 152 io_l16p_1/ldc1 151 io_l15 n _1/ldc0 150 io_l15p_1/hdc 149 v ccaux 14 8 ip 147 io_l14 n _1 146 io_l14p_1 145 io_l13 n _1 144 io_l13p_1 143 v cco_1 142 ip 141 g n d 140 io_l12 n _1/a0 139 io_l12p_1 13 8 io_l11 n _1/a1 137 io_l11p_1/a2 136 ip/ v ref_1 o_l10 n _1/a3/rhclk7 o_l10p_1/a4/rhclk6 o_l09 n _1/a5/rhclk5 o_l09p_1/a6/rhclk4 131 g n d 130 ip o_l0 8n _1/a7/rhclk3 o_l0 8 p_1/a 8 /rhclk2 o_l07 n _1/a9/rhclk1 o_l07p_1/a10/rhclk 125 v cco_1 124 ip 123 io_l06 n _1/ v ref_1 122 io_l06p_1 121 g n d 120 io_l05 n _1/a11 119 io_l05p_1/a12 11 8 ip 117 v cci n t 116 io_l04 n _1 115 io_l04p_1 114 v cco_1 113 io_l03 n _1/ v ref_1 112 io_l03p_1 111 v ccaux 110 ip 109 io_l02 n _1/a13 10 8 io_l02p_1/a14 107 io_l01 n _1/a15 106 io_l01p_1/a16 105 g n d 8 4 8 5 8 6 8 7 88 8 9 90 91 92 93 94 95 96 97 9 8 99 100 101 102 103 104 ip_l10p_2/rd w r_b/gclk0 ip_l10 n _2/m2/gclk1 io_l11p_2/d2/gclk2 io_l11 n _2/d1/gclk3 io/m1 g n d io_l12p_2/m0 io_l12 n _2/di n /d0 v cco_2 io_l13p_2 io_l13 n _2 ip v ccaux io_l14p_2/a23 io_l14 n _2/a22 g n d io_l15p_2/a21 io_l15 n _2/a20 io/ v ref_2 io_l16p_2/ v s2/a19 io_l16 n _2/ v s1/a1 8 ip io_l17p_2/ v s0/a17 io_l17 n _2/cclk do n e bank 1 bank 0 bank 2 8 0 8 1 8 2 8 3 126 i 127 i 12 8 i 129 i 132 i 133 i 134 i 135 i DS312-4_04_0 8 2009 pinout descriptions 192 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r ft256: 256-ball fine-pitch , thin ball grid array the 256-ball fine-pitch, thin ball grid array package, ft256, supports three different spartan-3e fpgas, including the xc3s250e, the xc3s500e, and the xc3s1200e. table 143 lists all the package pins. they are sorted by bank number and then by pin name of the largest device. pins that form a differential i/o pair appear together in the table. the table also shows the pin number for each pin and the pin type, as defined earlier. the highlighted rows indicate pinout differences between the xc3s250e, the xc3s500e, and the xc3s1200e fpgas. the xc3s250e has 18 unconnected balls, indi- cated as n.c. (no connection) in ta bl e 1 4 3 and with the black diamond character ( ) in table 143 and figure 86 . if the table row is highlighted in tan, then this is an instance where an unconnected pin on the xc3s250e fpga maps to a vref pin on the xc3s500e and xc3s1200e fpga. if the fpga application uses an i/o standard that requires a vref voltage reference, connect the highlighted pin to the vref voltage supply, even though this does not actually connect to the xc3s250e fp ga. this vref connection on the board allows future migration to the larger devices with- out modifying the printed-circuit board. all other balls have nearly identical functionality on all three devices. table 147 summarizes the spartan-3e footprint migration differences for the ft256 package. an electronic version of this package pinout table and foot- print diagram is available for download from the xilinx web site at: http://www.xilinx.com/support/doc umentation/data_sheets/s3e_pin.zip pinout table table 143: ft256 package pinout bank xc3s250e pin name xc3s500e pin name xc3s1200e pin name ft256 ball type 0 io io io a7 i/o 0 io io io a12 i/o 0 io io io b4 i/o 0 ip ip io b6 250e: input 500e: input 1200e: i/o 0 ip ip io b10 250e: input 500e: input 1200e: i/o 0 io/vref_0 io/vref_0 io/vref_0 d9 vref 0 io_l01n_0 io_l01n_0 io_l01n_0 a14 i/o 0 io_l01p_0 io_l01p_0 io_l01p_0 b14 i/o 0 io_l03n_0/vref_0 io_l03n_0/vref_0 io_l03n_0/vref_0 a13 vref 0 io_l03p_0 io_l03p_0 io_l03p_0 b13 i/o 0 io_l04n_0 io_l04n_0 io_l04n_0 e11 i/o 0 io_l04p_0 io_l04p_0 io_l04p_0 d11 i/o 0 io_l05n_0/vref_0 io_l05n_0/vref_0 io_l05n_0/vref_0 b11 vref 0 io_l05p_0 io_l05p_0 io_l05p_0 c11 i/o 0 io_l06n_0 io_l06n_0 io_l06n_0 e10 i/o 0 io_l06p_0 io_l06p_0 io_l06p_0 d10 i/o 0 io_l08n_0/gclk5 io_l08n_0/gclk5 io_l08n_0/gclk5 f9 gclk 0 io_l08p_0/gclk4 io_l08p_0/gclk4 io_l08p_0/gclk4 e9 gclk 0 io_l09n_0/gclk7 io_l09n_0/gclk7 io_l09n_0/gclk7 a9 gclk 0 io_l09p_0/gclk6 io_l09p_0/gclk6 io_l09p_0/gclk6 a10 gclk 0 io_l11n_0/gclk11 io_l11n_0/gclk11 io_l11n_0/gclk11 d8 gclk 0 io_l11p_0/gclk10 io_l11p_0/gclk10 io_l11p_0/gclk10 c8 gclk pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 193 product specification r 0 io_l12n_0 io_l12n_0 io_l12n_0 f8 i/o 0 io_l12p_0 io_l12p_0 io_l12p_0 e8 i/o 0 n.c. ( ) io_l13n_0 io_l13n_0 c7 250e: n.c. 500e: i/o 1200e: i/o 0 n.c. ( ) io_l13p_0 io_l13p_0 b7 250e: n.c. 500e: i/o 1200e: i/o 0 io_l14n_0/vref_0 io_l14n_0/vref_0 io_l14n_0/vref_0 d7 vref 0 io_l14p_0 io_l14p_0 io_l14p_0 e7 i/o 0 io_l15n_0 io_l15n_0 io_l15n_0 d6 i/o 0 io_l15p_0 io_l15p_0 io_l15p_0 c6 i/o 0 io_l17n_0/vref_0 io_l17n_0/vref_0 io_l17n_0/vref_0 a4 vref 0 io_l17p_0 io_l17p_0 io_l17p_0 a5 i/o 0 io_l18n_0 io_l18n_0 io_l18n_0 c4 i/o 0 io_l18p_0 io_l18p_0 io_l18p_0 c5 i/o 0 io_l19n_0/hswap io_l19n_0/hswap io_l19n_0/hswap b3 dual 0 io_l19p_0 io_l19p_0 io_l19p_0 c3 i/o 0 ip ip ip a3 input 0 ip ip ip c13 input 0 ip_l02n_0 ip_l02n_0 ip_l02n_0 c12 input 0 ip_l02p_0 ip_l02p_0 ip_l02p_0 d12 input 0 ip_l07n_0 ip_l07n_0 ip_l07n_0 c9 input 0 ip_l07p_0 ip_l07p_0 ip_l07p_0 c10 input 0 ip_l10n_0/gclk9 ip_l10n_0/gclk9 ip_l10n_0/gclk9 b8 gclk 0 ip_l10p_0/gclk8 ip_l10p_0/gclk8 ip_l10p_0/gclk8 a8 gclk 0 ip_l16n_0 ip_l16n_0 ip_l16n_0 e6 input 0 ip_l16p_0 ip_l16p_0 ip_l16p_0 d5 input 0 vcco_0 vcco_0 vcco_0 b5 vcco 0 vcco_0 vcco_0 vcco_0 b12 vcco 0 vcco_0 vcco_0 vcco_0 f7 vcco 0 vcco_0 vcco_0 vcco_0 f10 vcco 1 io_l01n_1/a15 io_l01n_1/a15 io_l01n_1/a15 r15 dual 1 io_l01p_1/a16 io_l01p_1/a16 io_l01p_1/a16 r16 dual 1 io_l02n_1/a13 io_l02n_1/a13 io_l02n_1/a13 p15 dual 1 io_l02p_1/a14 io_l02p_1/a14 io_l02p_1/a14 p16 dual 1 n.c. ( ) io_l03n_1/vref_1 io_l03n_1/vref_1 n15 250e: n.c. 500e: vref 1200e: vref 1 n.c. ( ) io_l03p_1 io_l03p_1 n14 250e: n.c. 500e: i/o 1200e: i/o table 143: ft256 package pinout (continued) bank xc3s250e pin name xc3s500e pin name xc3s1200e pin name ft256 ball type pinout descriptions 194 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r 1 io_l04n_1/vref_1 io_l04n_1/vref_1 io_l04n_1/vref_1 m16 vref 1 io_l04p_1 io_l04p_1 io_l04p_1 n16 i/o 1 n.c. ( ) io_l05n_1 io_l05n_1 l13 250e: n.c. 500e: i/o 1200e: i/o 1 n.c. ( ) io_l05p_1 io_l05p_1 l12 250e: n.c. 500e: i/o 1200e: i/o 1 io_l06n_1 io_l06n_1 io_l06n_1 l15 i/o 1 io_l06p_1 io_l06p_1 io_l06p_1 l14 i/o 1 io_l07n_1/a11 io_l07n_1/a11 io_l07n_1/a11 k12 dual 1 io_l07p_1/a12 io_l07p_1/a12 io_l07p_1/a12 k13 dual 1 io_l08n_1/vref_1 io_l08n_1/vref_1 io_l08n_1/vref_1 k14 vref 1 io_l08p_1 io_l08p_1 io_l08p_1 k15 i/o 1 io_l09n_1/a9/rhclk1 io_l09n_1/a9/rhclk1 io_l09n_1/a9/rhclk1 j16 rhclk/dual 1 io_l09p_1/a10/rhclk0 io_l09p_1/a10/rhclk0 io_l09p_1/a10/rhclk0 k16 rhclk/dual 1 io_l10n_1/a7/rhclk3/ trdy1 io_l10n_1/a7/rhclk3/ trdy1 io_l10n_1/a7/rhclk3/ trdy1 j13 rhclk/dual 1 io_l10p_1/a8/rhclk2 io_l10p_1/a8/rhclk2 io_l10p_1/a8/rhclk2 j14 rhclk/dual 1 io_l11n_1/a5/rhclk5 io_l11n_1/a5/rhclk5 io_l11n_1/a5/rhclk5 h14 rhclk/dual 1 io_l11p_1/a6/rhclk4/ irdy1 io_l11p_1/a6/rhclk4/ irdy1 io_l11p_1/a6/rhclk4/ irdy1 h15 rhclk/dual 1 io_l12n_1/a3/rhclk7 io_l12n_1/a3/rhclk7 io_l12n_1/a3/rhclk7 h11 rhclk/dual 1 io_l12p_1/a4/rhclk6 io_l12p_1/a4/rhclk6 io_l12p_1/a4/rhclk6 h12 rhclk/dual 1 io_l13n_1/a1 io_l13n_1/a1 io_l13n_1/a1 g16 dual 1 io_l13p_1/a2 io_l13p_1/a2 io_l13p_1/a2 g15 dual 1 io_l14n_1/a0 io_l14n_1/a0 io_l14n_1/a0 g14 dual 1 io_l14p_1 io_l14p_1 io_l14p_1 g13 i/o 1 io_l15n_1 io_l15n_1 io_l15n_1 f15 i/o 1 io_l15p_1 io_l15p_1 io_l15p_1 f14 i/o 1 io_l16n_1 io_l16n_1 io_l16n_1 f12 i/o 1 io_l16p_1 io_l16p_1 io_l16p_1 f13 i/o 1 n.c. ( ) io_l17n_1 io_l17n_1 e16 250e: n.c. 500e: i/o 1200e: i/o 1 n.c. ( ). io_l17p_1 io_l17p_1 e13 250e: n.c. 500e: i/o 1200e: i/o 1 io_l18n_1/ldc0 io_l18n_1/ldc0 io_l18n_1/ldc0 d14 dual 1 io_l18p_1/hdc io_l18p_1/hdc io_l18p_1/hdc d15 dual 1 io_l19n_1/ldc2 io_l19n_1/ldc2 io_l19n_1/ldc2 c15 dual 1 io_l19p_1/ldc1 io_l19p_1/ldc1 io_l19p_1/ldc1 c16 dual table 143: ft256 package pinout (continued) bank xc3s250e pin name xc3s500e pin name xc3s1200e pin name ft256 ball type pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 195 product specification r 1 ip ip ip b16 input 1 ip ip ip e14 input 1 ip ip ip g12 input 1 ip ip ip h16 input 1 ip ip ip j11 input 1 ip ip ip j12 input 1 ip ip ip m13 input 1 io io ip m14 250e: i/o 500e: i/o 1200e: input 1 io/vref_1 ip/vref_1 ip/vref_1 d16 250e: vref(i/o) 500e: vref(input) 1200e: vref(input) 1 ip/vref_1 ip/vref_1 ip/vref_1 h13 vref 1 vcco_1 vcco_1 vcco_1 e15 vcco 1 vcco_1 vcco_1 vcco_1 g11 vcco 1 vcco_1 vcco_1 vcco_1 k11 vcco 1 vcco_1 vcco_1 vcco_1 m15 vcco 2 ip ip io m7 250e: input 500e: input 1200e: i/o 2 ip ip io t12 250e: input 500e: input 1200e: i/o 2 io/d5 io/d5 io/d5 t8 dual 2 io/m1 io/m1 io/m1 t10 dual 2 io/vref_2 io/vref_2 io/vref_2 p13 vref 2 io/vref_2 io/vref_2 io/vref_2 r4 vref 2 io_l01n_2/init_b io_l01n_2/init_b io_l01n_2/init_b p4 dual 2 io_l01p_2/cso_b io_l01p_2/cso_b io_l01p_2/cso_b p3 dual 2 io_l03n_2/mosi/csi_b io_l03n_2/mosi/csi_b io_l03n_2/mosi/csi_b n5 dual 2 io_l03p_2/dout/busy io_l03p_2/dout/busy io_l03p_2/dout/busy p5 dual 2 io_l04n_2 io_l04n_2 io_l04n_2 t5 i/o 2 io_l04p_2 io_l04p_2 io_l04p_2 t4 i/o 2 io_l05n_2 io_l05n_2 io_l05n_2 n6 i/o 2 io_l05p_2 io_l05p_2 io_l05p_2 m6 i/o 2 io_l06n_2 io_l06n_2 io_l06n_2 p6 i/o 2 io_l06p_2 io_l06p_2 io_l06p_2 r6 i/o 2 n.c. ( ) io_l07n_2 io_l07n_2 p7 250e: n.c. 500e: i/o 1200e: i/o table 143: ft256 package pinout (continued) bank xc3s250e pin name xc3s500e pin name xc3s1200e pin name ft256 ball type pinout descriptions 196 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r 2 n.c. ( ) io_l07p_2 io_l07p_2 n7 250e: n.c. 500e: i/o 1200e: i/o 2 io_l09n_2/d6/gclk13 io_l09n_2/d6/gclk13 io_l09n_2/d6/gclk13 l8 dual/gclk 2 io_l09p_2/d7/gclk12 io_l09p_2/d7/gclk12 io_l09p_2/d7/gclk12 m8 dual/gclk 2 io_l10n_2/d3/gclk15 io_l10n_2/d3/gclk15 io_l10n_2/d3/gclk15 p8 dual/gclk 2 io_l10p_2/d4/gclk14 io_l10p_2/d4/gclk14 io_l10p_2/d4/gclk14 n8 dual/gclk 2 io_l12n_2/d1/gclk3 io_l12n_2/d1/gclk3 io_l12n_2/d1/gclk3 n9 dual/gclk 2 io_l12p_2/d2/gclk2 io_l12p_2/d2/gclk2 io_l12p_2/d2/gclk2 p9 dual/gclk 2 io_l13n_2/din/d0 io_l13n_2/din/d0 io_l13n_2/din/d0 m9 dual 2 io_l13p_2/m0 io_l13p_2/m0 io_l13p_2/m0 l9 dual 2 n.c. ( ) io_l14n_2/vref_2 io_l14n_2/vref_2 r10 250e: n.c. 500e: vref 1200e: vref 2 n.c. ( ) io_l14p_2 io_l14p_2 p10 250e: n.c. 500e: i/o 1200e: i/o 2 io_l15n_2 io_l15n_2 io_l15n_2 m10 i/o 2 io_l15p_2 io_l15p_2 io_l15p_2 n10 i/o 2 io_l16n_2/a22 io_l16n_2/a22 io_l16n_2/a22 p11 dual 2 io_l16p_2/a23 io_l16p_2/a23 io_l16p_2/a23 r11 dual 2 io_l18n_2/a20 io_l18n_2/a20 io_l18n_2/a20 n12 dual 2 io_l18p_2/a21 io_l18p_2/a21 io_l18p_2/a21 p12 dual 2 io_l19n_2/vs1/a18 io_l19n_2/vs1/a18 io_l19n_2/vs1/a18 r13 dual 2 io_l19p_2/vs2/a19 io_l19p_2/vs2/a19 io_l19p_2/vs2/a19 t13 dual 2 io_l20n_2/cclk io_l20n_2/cclk io_l20n_2/cclk r14 dual 2 io_l20p_2/vs0/a17 io_l20p_2/vs0/a17 io_l20p_2/vs0/a17 p14 dual 2 ip ip ip t2 input 2 ip ip ip t14 input 2 ip_l02n_2 ip_l02n_2 ip_l02n_2 r3 input 2 ip_l02p_2 ip_l02p_2 ip_l02p_2 t3 input 2 ip_l08n_2/vref_2 ip_l08n_2/vref_2 ip_l08n_2/vref_2 t7 vref 2 ip_l08p_2 ip_l08p_2 ip_l08p_2 r7 input 2 ip_l11n_2/m2/gclk1 ip_l11n_2/m2/gclk1 ip_l11n_2/m2/gclk1 r9 dual/gclk 2 ip_l11p_2/rdwr_b/ gclk0 ip_l11p_2/rdwr_b/ gclk0 ip_l11p_2/rdwr_b/ gclk0 t9 dual/gclk 2 ip_l17n_2 ip_l17n_2 ip_l17n_2 m11 input 2 ip_l17p_2 ip_l17p_2 ip_l17p_2 n11 input 2 vcco_2 vcco_2 vcco_2 l7 vcco 2 vcco_2 vcco_2 vcco_2 l10 vcco 2 vcco_2 vcco_2 vcco_2 r5 vcco 2 vcco_2 vcco_2 vcco_2 r12 vcco table 143: ft256 package pinout (continued) bank xc3s250e pin name xc3s500e pin name xc3s1200e pin name ft256 ball type pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 197 product specification r 3 io_l01n_3 io_l01n_3 io_l01n_3 b2 i/o 3 io_l01p_3 io_l01p_3 io_l01p_3 b1 i/o 3 io_l02n_3/vref_3 io_l02n_3/vref_3 io_l02n_3/vref_3 c2 vref 3 io_l02p_3 io_l02p_3 io_l02p_3 c1 i/o 3 io_l03n_3 io_l03n_3 io_l03n_3 e4 i/o 3 io_l03p_3 io_l03p_3 io_l03p_3 e3 i/o 3 n.c. ( ) io_l04n_3/vref_3 io_l04n_3/vref_3 f4 250e: n.c. 500e: vref 1200e: vref 3 n.c. ( ) io_l04p_3 io_l04p_3 f3 250e: n.c. 500e: i/o 1200e: i/o 3 io_l05n_3 io_l05n_3 io_l05n_3 e1 i/o 3 io_l05p_3 io_l05p_3 io_l05p_3 d1 i/o 3 io_l06n_3 io_l06n_3 io_l06n_3 g4 i/o 3 io_l06p_3 io_l06p_3 io_l06p_3 g5 i/o 3 io_l07n_3 io_l07n_3 io_l07n_3 g2 i/o 3 io_l07p_3 io_l07p_3 io_l07p_3 g3 i/o 3 io_l08n_3/lhclk1 io_l08n_3/lhclk1 io_l08n_3/lhclk1 h6 lhclk 3 io_l08p_3/lhclk0 io_l08p_3/lhclk0 io_l08p_3/lhclk0 h5 lhclk 3 io_l09n_3/lhclk3/ irdy2 io_l09n_3/lhclk3/ irdy2 io_l09n_3/lhclk3/ irdy2 h4 lhclk 3 io_l09p_3/lhclk2 io_l09p_3/lhclk2 io_l09p_3/lhclk2 h3 lhclk 3 io_l10n_3/lhclk5 io_l10n_3/lhclk5 io_l10n_3/lhclk5 j3 lhclk 3 io_l10p_3/lhclk4/ trdy2 io_l10p_3/lhclk4/ trdy2 io_l10p_3/lhclk4/ trdy2 j2 lhclk 3 io_l11n_3/lhclk7 io_l11n_3/lhclk7 io_l11n_3/lhclk7 j4 lhclk 3 io_l11p_3/lhclk6 io_l11p_3/lhclk6 io_l11p_3/lhclk6 j5 lhclk 3 io_l12n_3 io_l12n_3 io_l12n_3 k1 i/o 3 io_l12p_3 io_l12p_3 io_l12p_3 j1 i/o 3 io_l13n_3 io_l13n_3 io_l13n_3 k3 i/o 3 io_l13p_3 io_l13p_3 io_l13p_3 k2 i/o 3 n.c. ( ) io_l14n_3/vref_3 io_l14n_3/vref_3 l2 250e: n.c. 500e: vref 1200e: vref 3 n.c. ( ) io_l14p_3 io_l14p_3 l3 250e: n.c. 500e: i/o 1200e: i/o 3 io_l15n_3 io_l15n_3 io_l15n_3 l5 i/o 3 io_l15p_3 io_l15p_3 io_l15p_3 k5 i/o 3 io_l16n_3 io_l16n_3 io_l16n_3 n1 i/o 3 io_l16p_3 io_l16p_3 io_l16p_3 m1 i/o table 143: ft256 package pinout (continued) bank xc3s250e pin name xc3s500e pin name xc3s1200e pin name ft256 ball type pinout descriptions 198 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r 3 n.c. ( ) io_l17n_3 io_l17n_3 l4 250e: n.c. 500e: i/o 1200e: i/o 3 n.c. ( ) io_l17p_3 io_l17p_3 m4 250e: n.c. 500e: i/o 1200e: i/o 3 io_l18n_3 io_l18n_3 io_l18n_3 p1 i/o 3 io_l18p_3 io_l18p_3 io_l18p_3 p2 i/o 3 io_l19n_3 io_l19n_3 io_l19n_3 r1 i/o 3 io_l19p_3 io_l19p_3 io_l19p_3 r2 i/o 3 ip ip ip d2 input 3 ip ip ip f2 input 3 io io ip f5 250e: i/o 500e: i/o 1200e: input 3 ip ip ip h1 input 3 ip ip ip j6 input 3 ip ip ip k4 input 3 ip ip ip m3 input 3 ip ip ip n3 input 3 ip/vref_3 ip/vref_3 ip/vref_3 g1 vref 3 io/vref_3 io/vref_3 ip/vref_3 n2 250e: vref(i/o) 500e: vref(i/o) 1200e: vref(input) 3 vcco_3 vcco_3 vcco_3 e2 vcco 3 vcco_3 vcco_3 vcco_3 g6 vcco 3 vcco_3 vcco_3 vcco_3 k6 vcco 3 vcco_3 vcco_3 vcco_3 m2 vcco gnd gnd gnd gnd a1 gnd gnd gnd gnd gnd a16 gnd gnd gnd gnd gnd b9 gnd gnd gnd gnd gnd f6 gnd gnd gnd gnd gnd f11 gnd gnd gnd gnd gnd g7 gnd gnd gnd gnd gnd g8 gnd gnd gnd gnd gnd g9 gnd gnd gnd gnd gnd g10 gnd gnd gnd gnd gnd h2 gnd gnd gnd gnd gnd h7 gnd gnd gnd gnd gnd h8 gnd gnd gnd gnd gnd h9 gnd table 143: ft256 package pinout (continued) bank xc3s250e pin name xc3s500e pin name xc3s1200e pin name ft256 ball type pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 199 product specification r gnd gnd gnd gnd h10 gnd gnd gnd gnd gnd j7 gnd gnd gnd gnd gnd j8 gnd gnd gnd gnd gnd j9 gnd gnd gnd gnd gnd j10 gnd gnd gnd gnd gnd j15 gnd gnd gnd gnd gnd k7 gnd gnd gnd gnd gnd k8 gnd gnd gnd gnd gnd k9 gnd gnd gnd gnd gnd k10 gnd gnd gnd gnd gnd l6 gnd gnd gnd gnd gnd l11 gnd gnd gnd gnd gnd r8 gnd gnd gnd gnd gnd t1 gnd gnd gnd gnd gnd t16 gnd vccaux done done done t15 config vccaux prog_b prog_b prog_b d3 config vccaux tck tck tck a15 jtag vccaux tdi tdi tdi a2 jtag vccaux tdo tdo tdo c14 jtag vccaux tms tms tms b15 jtag vccaux vccaux vccaux vccaux a6 vccaux vccaux vccaux vccaux vccaux a11 vccaux vccaux vccaux vccaux vccaux f1 vccaux vccaux vccaux vccaux vccaux f16 vccaux vccaux vccaux vccaux vccaux l1 vccaux vccaux vccaux vccaux vccaux l16 vccaux vccaux vccaux vccaux vccaux t6 vccaux vccaux vccaux vccaux vccaux t11 vccaux vccint vccint vccint vccint d4 vccint vccint vccint vccint vccint d13 vccint vccint vccint vccint vccint e5 vccint vccint vccint vccint vccint e12 vccint vccint vccint vccint vccint m5 vccint vccint vccint vccint vccint m12 vccint vccint vccint vccint vccint n4 vccint vccint vccint vccint vccint n13 vccint table 143: ft256 package pinout (continued) bank xc3s250e pin name xc3s500e pin name xc3s1200e pin name ft256 ball type pinout descriptions 200 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r user i/os by bank table 144 , ta bl e 1 4 5 , and table 146 indicate how the avail- able user-i/o pins are distributed between the four i/o banks on the ft256 package. the xc3s250e fpga in the ft256 package has 18 uncon- nected balls, labeled with an ?n.c.? type. these pins are also indicated with the black diamond ( ) symbol in figure 86 . . table 144: user i/os per bank on xc3s250e in the ft256 package package edge i/o bank maximum i/o all possible i/o pins by type i/o input dual vref (1) clk (1) to p 0 44 20 10 1 5 8 right 1 42 10 7 21 4 0 (2) bottom 2 44 8 9 24 3 0 (2) left 3 42 24 7 0 3 8 total 172 62 33 46 15 16 notes: 1. some vref and clk pins are on input pins. 2. the eight global clock pins in this bank have optional functionality during configuration and are counted in the dual column. table 145: user i/os per bank on xc3s500e in the ft256 package package edge i/o bank maximum i/o all possible i/o pins by type i/o input dual vref (1) clk (1) to p 0 46 22 10 1 5 8 right 1 48 15 7 21 5 0 (2) bottom 2 48 11 9 24 4 0 (2) left 3 48 28 7 0 5 8 total 190 76 33 46 19 16 notes: 1. some vref and clk pins are on input pins. 2. the eight global clock pins in this bank have optional functionality during configuration and are counted in the dual column. table 146: user i/os per bank on xc3s1200e in the ft256 package package edge i/o bank maximum i/o all possible i/o pins by type i/o input dual vref (1) clk (1) to p 0 46 24 8 1 5 8 right 1 48 14 8 21 5 0 (2) bottom 2 48 13 7 24 4 0 (2) left 3 48 27 8 0 5 8 total 190 78 31 46 19 16 notes: 1. some vref and clk pins are on input pins. 2. the eight global clock pins in this bank have optional functionality during configuration and are counted in the dual column. pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 201 product specification r footprint migration differences table 147 summarizes any footprint and functionality differ- ences between the xc3s250e, the xc3s500e, and the xc3s1200e fpgas that may affect easy migration between devices in the fg256 package. there are 26 such balls. all other pins not listed in ta bl e 1 4 7 unconditionally migrate between spartan-3e devices available in the ft256 package. the xc3s250e is duplicated on both the left and right sides of the table to show migrations to and from the xc3s500e and the xc3s1200e. the arrows indicate the direction for easy migration. a double-ended arrow ( ) indicates that the two pins have identical functionality. a left-facing arrow ( ) indicates that the pin on the device on the right uncon- ditionally migrates to the pin on the device on the left. it may be possible to migrate the opposite direction depending on the i/o configuration. for example, an i/o pin (type = i/o) can migrate to an input-only pin (type = input) if the i/o pin is configured as an input. table 147: ft256 footprint migration differences ft256 ball bank xc3s250e type migration xc3s500e type migration xc3s1200e type migration xc3s250e type b6 0 input input i/o input b7 0 n.c. i/o i/o n.c. b10 0 input input i/o input c7 0 n.c. i/o i/o n.c. d16 1 vref(i/o) vref(input) vref(input) vref(i/o) e13 1 n.c. i/o i/o n.c. e16 1 n.c. i/o i/o n.c. f3 3 n.c. i/o i/o n.c. f4 3 n.c. vref vref n.c. f5 3 i/o i/o input i/o l2 3 n.c. vref vref n.c. l3 3 n.c. i/o i/o n.c. l4 3 n.c. i/o i/o n.c. l12 1 n.c. i/o i/o n.c. l13 1 n.c. i/o i/o n.c. m4 3 n.c. i/o i/o n.c. m7 2 input input i/o input m14 1 i/o i/o input i/o n2 3 vref(i/o) vref(i/o) vref(input) vref(i/o) n7 2 n.c. i/o i/o n.c. n14 1 n.c. i/o i/o n.c. n15 1 n.c. vref vref n.c. p7 2 n.c. i/o i/o n.c. p10 2 n.c. i/o i/o n.c. r10 2 n.c. vref vref n.c. t12 2 input input i/o input differences 19 7 26 legend: this pin is identical on the device on the left and the right. this pin can unconditionally migrat e from the device on the left to the device on the right. migration in the other direction m ay be possible depending on how the pin is configured for the device on the right. this pin can unconditionally migr ate from the device on the right to the device on the left. migration in the other direction m ay be possible depending on how the pin is configured for the device on the left. pinout descriptions 202 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r ft256 footprint figure 86: ft256 package footprint (top view) 12345678910111213141516 a gnd tdi input i/o l17n_0 vref_0 i/o l17p_0 vccaux i/o input l10p_0 gclk8 i/o l09n_0 gclk7 i/o l09p_0 gclk6 vccaux i/o i/o l03n_0 vref_0 i/o l01n_0 tck gnd b i/o l01p_3 i/o l01n_3 i/o l19n_0 hswap i/o vcco_0 input ? ? ? ? ? ? ? ? i/o l13p_0 ? input l10n_0 gclk9 gnd input ? ? ? ? ? ? ? ? i/o l05n_0 vref_0 vcco_0 i/o l03p_0 i/o l01p_0 tms input c i/o l02p_3 i/o l02n_3 vref_3 i/o l19p_0 i/o l18n_0 i/o l18p_0 i/o l15p_0 i/o l13n_0 ? i/o l11p_0 gclk10 input l07n_0 input l07p_0 i/o l05p_0 input l02n_0 input tdo i/o l19n_1 ldc2 i/o l19p_1 ldc1 d i/o l05p_3 input prog_b vccint input l16p_0 i/o l15n_0 i/o l14n_0 vref_0 i/o l11n_0 gclk11 i/o vref_0 i/o l06p_0 i/o l04p_0 input l02p_0 vccint i/o l18n_1 ldc0 i/o l18p_1 hdc input vref_1 ? ? e i/o l05n_3 vcco_3 i/o l03p_3 i/o l03n_3 vccint input l16n_0 i/o l14p_0 i/o l12p_0 i/o l08p_0 gclk4 i/o l06n_0 i/o l04n_0 vccint i/o l17p_1 ? input vcco_1 i/o l17n_1 ? f vccaux input i/o l04p_3 ? i/o l04n_3 vref_3 ? input ? ? ? ? ? ? ? ? gnd vcco_0 i/o l12n_0 i/o l08n_0 gclk5 vcco_0 gnd i/o l16n_1 i/o l16p_1 i/o l15p_1 i/o l15n_1 vccaux g input vref_3 i/o l07n_3 i/o l07p_3 i/o l06n_3 i/o l06p_3 vcco_3 gnd gnd gnd gnd vcco_1 input i/o l14p_1 i/o l14n_1 a0 i/o l13p_1 a2 i/o l13n_1 a1 h input gnd i/o l09p_3 lhclk2 i/o l09n_3 lhclk3 irdy2 i/o l08p_3 lhclk0 i/o l08n_3 lhclk1 gnd gnd gnd gnd input vref_1 input j i/o l12p_3 i/o l10p_3 lhclk4 trdy2 i/o l10n_3 lhclk5 i/o l11n_3 lhclk7 i/o l11p_3 lhclk6 input gnd gnd gnd gnd input input gnd k i/o l12n_3 i/o l13p_3 i/o l13n_3 input i/o l15p_3 vcco_3 gnd gnd gnd gnd vcco_1 i/o l07n_1 a11 i/o l07p_1 a12 i/o l08n_1 vref_1 i/o l08p_1 l vccaux i/o l14n_3 vref_3 ? i/o l14p_3 ? i/o l17n_3 ? i/o l15n_3 gnd vcco_2 i/o l13p_2 m0 vcco_2 gnd i/o l05p_1 ? i/o l05n_1 ? i/o l06p_1 i/o l06n_1 vccaux m i/o l16p_3 vcco_3 input i/o l17p_3 ? vccint i/o l05p_2 input ? ? ? ? ? ? ? ? i/o l13n_2 din d0 i/o l15n_2 input l17n_2 vccint input input ? ? ? ? ? ? ? ? vcco_1 i/o l04n_1 vref_1 n i/o l16n_3 input vref_3 ? ? input vccint i/o l03n_2 mosi csi_b i/o l05n_2 i/o l07p_2 ? i/o l15p_2 input l17p_2 i/o l18n_2 a20 vccint i/o l03p_1 ? i/o l03n_1 vref_1 ? i/o l04p_1 p i/o l18n_3 i/o l18p_3 i/o l01p_2 cso_b i/o l01n_2 init_b i/o l03p_2 dout busy i/o l06n_2 i/o l07n_2 ? i/o l14p_2 ? i/o l16n_2 a22 i/o l18p_2 a21 i/o vref_2 i/o l20p_2 vs0 a 17 i/o l02n_1 a13 i/o l02p_1 a14 r i/o l19n_3 i/o l19p_3 input l02n_2 i/o vref_2 vcco_2 i/o l06p_2 input l08p_2 gnd i/o l14n_2 vref_2 ? i/o l16p_2 a23 vcco_2 i/o l19n_2 vs1 a 18 i/o l20n_2 cclk i/o l01n_1 a15 i/o l01p_1 a16 t gnd input input l02p_2 i/o l04p_2 i/o l04n_2 vccaux input l08n_2 vref_2 i/o d5 i/o m1 vccaux input ? ? ? ? ? ? ? ? i/o l19p_2 vs2 a 19 input done gnd bank 3 bank 1 bank 0 bank 2 i/o l12n_1 3 rhclk7 a i/o l12p_1 rhclk6 a 4 i/o l10n_1 a rhclk3 7 trdy1 i/o l11n_1 a 5 rhclk5 i/o l10p_1 a 8 rhclk2 i/o l11p_1 6 rhclk4 irdy1 a i/o l09n_1 a 9 rhclk1 i/o l09p_1 a 10 rhclk0 i/o l09p_2 d7 gclk12 i/o l09n_2 gclk13 d6 i/o l10p_2 d4 gclk14 i/o l12n_2 d1 gclk3 i/o l10n_2 d3 gclk15 i/o l12p_2 d2 gclk2 gclk1 m2 input l11n_2 gclk0 rdwr_b l11p_2 input DS312-4_05_101805 2 config: dedicated configuration pins 4 jtag: dedicated jtag port pins 8 vccint: internal core supply voltage (+1.2v) 28 gnd: ground 16 vcco: output voltage supply for bank 8 vccaux: auxiliary supply voltage (+2.5v) 6 migration difference: for flexible package migration, use these pins as inputs. 18 ( ) unconnected pins on xc3s250e pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 203 product specification r fg320: 320-ball fine-p itch ball grid array the 320-ball fine-pitch ball grid array package, fg320, sup- ports three different spartan-3e fpgas, including the xc3s500e, the xc3s1200e, and the xc3s1600e, as shown in ta b l e 1 4 8 and figure 87 . the fg320 package is an 18 x 18 array of solder balls minus the four center balls. table 148 lists all the package pins. they are sorted by bank number and then by pin name of the largest device. pins that form a differential i/o pair appear together in the table. the table also shows the pin number for each pin and the pin type, as defined earlier. the highlighted rows indicate pinout differences between the xc3s500e, the xc3s1200e, and the xc3s1600e fpgas. the xc3s500e has 18 unconnected balls, indi- cated as n.c. (no connection) in ta bl e 1 4 8 and with the black diamond character ( ) in table 148 and figure 87 . if the table row is highlighted in tan, then this is an instance where an unconnected pin on the xc3s500e fpga maps to a vref pin on the xc3s1200e and xc3s1600e fpga. if the fpga application uses an i/o standard that requires a vref voltage reference, connect the highlighted pin to the vref voltage supply, even though this does not actually connect to the xc3s500e fp ga. this vref connection on the board allows future migration to the larger devices with- out modifying the printed-circuit board. all other balls have nearly identical functionality on all three devices. table 147 summarizes the spartan-3e footprint migration differences for the fg320 package. an electronic version of this package pinout table and foot- print diagram is available for download from the xilinx web site at: http://www.xilinx.com/support/doc umentation/data_sheets/s3e_pin.zip pinout table table 148: fg320 package pinout bank xc3s500e pin name xc3s1200e pin name xc3s1600e pin name fg320 ball type 0 ip io io a7 500e: input 1200e: i/o 1600e: i/o 0 io io io a8 i/o 0 io io io a11 i/o 0 n.c. ( ) io io a12 500e: n.c. 1200e: i/o 1600e: i/o 0 io io io c4 i/o 0 ip io io d13 500e: input 1200e: i/o 1600e: i/o 0 io io io e13 i/o 0 io io io g9 i/o 0 io/vref_0 io/vref_0 io/vref_0 b11 vref 0 io_l01n_0 io_l01n_0 io_l01n_0 a16 i/o 0 io_l01p_0 io_l01p_0 io_l01p_0 b16 i/o 0 io_l03n_0/vref_0 io_l03n_0/vref_0 io_l03n_0/vref_0 c14 vref 0 io_l03p_0 io_l03p_0 io_l03p_0 d14 i/o 0 io_l04n_0 io_l04n_0 io_l04n_0 a14 i/o 0 io_l04p_0 io_l04p_0 io_l04p_0 b14 i/o 0 io_l05n_0/vref_0 io_l05n_0/vref_0 io_l05n_0/vref_0 b13 vref 0 io_l05p_0 io_l05p_0 io_l05p_0 a13 i/o 0 io_l06n_0 io_l06n_0 io_l06n_0 e12 i/o 0 io_l06p_0 io_l06p_0 io_l06p_0 f12 i/o pinout descriptions 204 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r 0 io_l08n_0 io_l08n_0 io_l08n_0 f11 i/o 0 io_l08p_0 io_l08p_0 io_l08p_0 e11 i/o 0 io_l09n_0 io_l09n_0 io_l09n_0 d11 i/o 0 io_l09p_0 io_l09p_0 io_l09p_0 c11 i/o 0 io_l11n_0/gclk5 io_l11n_0/gclk5 io_l11n_0/gclk5 e10 gclk 0 io_l11p_0/gclk4 io_l11p_0/gclk4 io_l11p_0/gclk4 d10 gclk 0 io_l12n_0/gclk7 io_l12n_0/gclk7 io_l12n_0/gclk7 a10 gclk 0 io_l12p_0/gclk6 io_l12p_0/gclk6 io_l12p_0/gclk6 b10 gclk 0 io_l14n_0/gclk11 io_l14n_0/gclk11 io_l14n_0/gclk11 d9 gclk 0 io_l14p_0/gclk10 io_l14p_0/gclk10 io_l14p_0/gclk10 c9 gclk 0 io_l15n_0 io_l15n_0 io_l15n_0 f9 i/o 0 io_l15p_0 io_l15p_0 io_l15p_0 e9 i/o 0 io_l17n_0 io_l17n_0 io_l17n_0 f8 i/o 0 io_l17p_0 io_l17p_0 io_l17p_0 e8 i/o 0 io_l18n_0/vref_0 io_l18n_0/vref_0 io_l18n_0/vref_0 d7 vref 0 io_l18p_0 io_l18p_0 io_l18p_0 c7 i/o 0 io_l19n_0/vref_0 io_l19n_0/vref_0 io_l19n_0/vref_0 e7 vref 0 io_l19p_0 io_l19p_0 io_l19p_0 f7 i/o 0 io_l20n_0 io_l20n_0 io_l20n_0 a6 i/o 0 io_l20p_0 io_l20p_0 io_l20p_0 b6 i/o 0 n.c. ( ) io_l21n_0 io_l21n_0 e6 500e: n.c. 1200e: i/o 1600e: i/o 0 n.c. ( ) io_l21p_0 io_l21p_0 d6 500e: n.c. 1200e: i/o 1600e: i/o 0 io_l23n_0/vref_0 io_l23n_0/vref_0 io_l23n_0/vref_0 d5 vref 0 io_l23p_0 io_l23p_0 io_l23p_0 c5 i/o 0 io_l24n_0 io_l24n_0 io_l24n_0 b4 i/o 0 io_l24p_0 io_l24p_0 io_l24p_0 a4 i/o 0 io_l25n_0/hswap io_l25n_0/hswap io_l25n_0/hswap b3 dual 0 io_l25p_0 io_l25p_0 io_l25p_0 c3 i/o 0 ip ip ip a3 input 0 ip ip ip c15 input 0 ip_l02n_0 ip_l02n_0 ip_l02n_0 a15 input 0 ip_l02p_0 ip_l02p_0 ip_l02p_0 b15 input 0 ip_l07n_0 ip_l07n_0 ip_l07n_0 d12 input 0 ip_l07p_0 ip_l07p_0 ip_l07p_0 c12 input 0 ip_l10n_0 ip_l10n_0 ip_l10n_0 g10 input 0 ip_l10p_0 ip_l10p_0 ip_l10p_0 f10 input 0 ip_l13n_0/gclk9 ip_l13n_0/gclk9 ip_l13n_0/gclk9 b9 gclk table 148: fg320 package pinout (continued) bank xc3s500e pin name xc3s1200e pin name xc3s1600e pin name fg320 ball type pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 205 product specification r 0 ip_l13p_0/gclk8 ip_l13p_0/gclk8 ip_l13p_0/gclk8 b8 gclk 0 ip_l16n_0 ip_l16n_0 ip_l16n_0 d8 input 0 ip_l16p_0 ip_l16p_0 ip_l16p_0 c8 input 0 ip_l22n_0 ip_l22n_0 ip_l22n_0 b5 input 0 ip_l22p_0 ip_l22p_0 ip_l22p_0 a5 input 0 vcco_0 vcco_0 vcco_0 a9 vcco 0 vcco_0 vcco_0 vcco_0 c6 vcco 0 vcco_0 vcco_0 vcco_0 c13 vcco 0 vcco_0 vcco_0 vcco_0 g8 vcco 0 vcco_0 vcco_0 vcco_0 g11 vcco 1 n.c. ( ) io io p16 500e: n.c. 1200e: i/o 1600e: i/o 1 io_l01n_1/a15 io_l01n_1/a15 io_l01n_1/a15 t17 dual 1 io_l01p_1/a16 io_l01p_1/a16 io_l01p_1/a16 u18 dual 1 io_l02n_1/a13 io_l02n_1/a13 io_l02n_1/a13 t18 dual 1 io_l02p_1/a14 io_l02p_1/a14 io_l02p_1/a14 r18 dual 1 io_l03n_1/vref_1 io_l03n_1/vref_1 io_l03n_1/vref_1 r16 vref 1 io_l03p_1 io_l03p_1 io_l03p_1 r15 i/o 1 n.c. ( ) io_l04n_1 io_l04n_1 n14 500e: n.c. 1200e: i/o 1600e: i/o 1 n.c. ( ) io_l04p_1 io_l04p_1 n15 500e: n.c. 1200e: i/o 1600e: i/o 1 io_l05n_1/vref_1 io_l05n_1/vref_1 io_l05n_1/vref_1 m13 vref 1 io_l05p_1 io_l05p_1 io_l05p_1 m14 i/o 1 io_l06n_1 io_l06n_1 io_l06n_1 p18 i/o 1 io_l06p_1 io_l06p_1 io_l06p_1 p17 i/o 1 io_l07n_1 io_l07n_1 io_l07n_1 m16 i/o 1 io_l07p_1 io_l07p_1 io_l07p_1 m15 i/o 1 io_l08n_1 io_l08n_1 io_l08n_1 m18 i/o 1 io_l08p_1 io_l08p_1 io_l08p_1 n18 i/o 1 io_l09n_1/a11 io_l09n_1/a11 io_l09n_1/a11 l15 dual 1 io_l09p_1/a12 io_l09p_1/a12 io_l09p_1/a12 l16 dual 1 io_l10n_1/vref_1 io_l10n_1/vref_1 io_l10n_1/vref_1 l17 vref 1 io_l10p_1 io_l10p_1 io_l10p_1 l18 i/o 1 io_l11n_1/a9/rhclk1 io_l11n_1/a9/rhclk1 io_l11n_1/a9/rhclk1 k12 rhclk/dual 1 io_l11p_1/a10/rhclk0 io_l11p_1/a10/rhclk0 io_l11p_1/a10/rhclk0 k13 rhclk/dual 1 io_l12n_1/a7/rhclk3/ trdy1 io_l12n_1/a7/rhclk3/ trdy1 io_l12n_1/a7/rhclk3/ trdy1 k14 rhclk/dual 1 io_l12p_1/a8/rhclk2 io_l12p_1/a8/rhclk2 io_l12p_1/a8/rhclk2 k15 rhclk/dual table 148: fg320 package pinout (continued) bank xc3s500e pin name xc3s1200e pin name xc3s1600e pin name fg320 ball type pinout descriptions 206 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r 1 io_l13n_1/a5/rhclk5 io_l13n_1/a5/rhclk5 io_l13n_1/a5/rhclk5 j16 rhclk/dual 1 io_l13p_1/a6/rhclk4/ irdy1 io_l13p_1/a6/rhclk4/ irdy1 io_l13p_1/a6/rhclk4/ irdy1 j17 rhclk/dual 1 io_l14n_1/a3/rhclk7 io_l14n_1/a3/rhclk7 io_l14n_1/a3/rhclk7 j14 rhclk/dual 1 io_l14p_1/a4/rhclk6 io_l14p_1/a4/rhclk6 io_l14p_1/a4/rhclk6 j15 rhclk/dual 1 io_l15n_1/a1 io_l15n_1/a1 io_l15n_1/a1 j13 dual 1 io_l15p_1/a2 io_l15p_1/a2 io_l15p_1/a2 j12 dual 1 io_l16n_1/a0 io_l16n_1/a0 io_l16n_1/a0 h17 dual 1 io_l16p_1 io_l16p_1 io_l16p_1 h16 i/o 1 io_l17n_1 io_l17n_1 io_l17n_1 h15 i/o 1 io_l17p_1 io_l17p_1 io_l17p_1 h14 i/o 1 io_l18n_1 io_l18n_1 io_l18n_1 g16 i/o 1 io_l18p_1 io_l18p_1 io_l18p_1 g15 i/o 1 io_l19n_1 io_l19n_1 io_l19n_1 f17 i/o 1 io_l19p_1 io_l19p_1 io_l19p_1 f18 i/o 1 io_l20n_1 io_l20n_1 io_l20n_1 g13 i/o 1 io_l20p_1 io_l20p_1 io_l20p_1 g14 i/o 1 io_l21n_1 io_l21n_1 io_l21n_1 f14 i/o 1 io_l21p_1 io_l21p_1 io_l21p_1 f15 i/o 1 n.c. ( ) io_l22n_1 io_l22n_1 e16 500e: n.c. 1200e: i/o 1600e: i/o 1 n.c. ( ) io_l22p_1 io_l22p_1 e15 500e: n.c. 1200e: i/o 1600e: i/o 1 io_l23n_1/ldc0 io_l23n_1/ldc0 io_l23n_1/ldc0 d16 dual 1 io_l23p_1/hdc io_l23p_1/hdc io_l23p_1/hdc d17 dual 1 io_l24n_1/ldc2 io_l24n_1/ldc2 io_l24n_1/ldc2 c17 dual 1 io_l24p_1/ldc1 io_l24p_1/ldc1 io_l24p_1/ldc1 c18 dual 1 ip ip ip b18 input 1 io ip ip e17 500e: i/o 1200e: input 1600e: input 1 ip ip ip e18 input 1 ip ip ip g18 input 1 ip ip ip h13 input 1 ip ip ip k17 input 1 ip ip ip k18 input 1 ip ip ip l13 input 1 ip ip ip l14 input 1 ip ip ip n17 input table 148: fg320 package pinout (continued) bank xc3s500e pin name xc3s1200e pin name xc3s1600e pin name fg320 ball type pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 207 product specification r 1 io ip ip p15 500e: i/o 1200e: input 1600e: input 1 ip ip ip r17 input 1 ip/vref_1 ip/vref_1 ip/vref_1 d18 vref 1 ip/vref_1 ip/vref_1 ip/vref_1 h18 vref 1 vcco_1 vcco_1 vcco_1 f16 vcco 1 vcco_1 vcco_1 vcco_1 h12 vcco 1 vcco_1 vcco_1 vcco_1 j18 vcco 1 vcco_1 vcco_1 vcco_1 l12 vcco 1 vcco_1 vcco_1 vcco_1 n16 vcco 2 io io io p9 i/o 2 io io io r11 i/o 2 ip io io u6 500e: input 1200e: i/o 1600e: i/o 2 ip io io u13 500e: input 1200e: i/o 1600e: i/o 2 n.c. ( ) io io v7 500e: n.c. 1200e: i/o 1600e: i/o 2 io/d5 io/d5 io/d5 r9 dual 2 io/m1 io/m1 io/m1 v11 dual 2 io/vref_2 io/vref_2 io/vref_2 t15 vref 2 io/vref_2 io/vref_2 io/vref_2 u5 vref 2 io_l01n_2/init_b io_l01n_2/init_b io_l01n_2/init_b t3 dual 2 io_l01p_2/cso_b io_l01p_2/cso_b io_l01p_2/cso_b u3 dual 2 io_l03n_2/mosi/csi_b io_l03n_2/mosi/csi_b io_l03n_2/mosi/csi_b t4 dual 2 io_l03p_2/dout/busy io_l03p_2/dout/busy io_l03p_2/dout/busy u4 dual 2 io_l04n_2 io_l04n_2 io_l04n_2 t5 i/o 2 io_l04p_2 io_l04p_2 io_l04p_2 r5 i/o 2 io_l05n_2 io_l05n_2 io_l05n_2 p6 i/o 2 io_l05p_2 io_l05p_2 io_l05p_2 r6 i/o 2 n.c. ( ) io_l06n_2/vref_2 io_l06n_2/vref_2 v6 500e: n.c. 1200e: vref 1600e: vref 2 n.c. ( ) io_l06p_2 io_l06p_2 v5 500e: n.c. 1200e: i/o 1600e: i/o 2 io_l07n_2 io_l07n_2 io_l07n_2 p7 i/o 2 io_l07p_2 io_l07p_2 io_l07p_2 n7 i/o table 148: fg320 package pinout (continued) bank xc3s500e pin name xc3s1200e pin name xc3s1600e pin name fg320 ball type pinout descriptions 208 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r 2 io_l09n_2 io_l09n_2 io_l09n_2 n8 i/o 2 io_l09p_2 io_l09p_2 io_l09p_2 p8 i/o 2 io_l10n_2 io_l10n_2 io_l10n_2 t8 i/o 2 io_l10p_2 io_l10p_2 io_l10p_2 r8 i/o 2 io_l12n_2/d6/gclk13 io_l12n_2/d6/gclk13 io_l12n_2/d6/gclk13 m9 dual/gclk 2 io_l12p_2/d7/gclk12 io_l12p_2/d7/gclk12 io_l12p_2/d7/gclk12 n9 dual/gclk 2 io_l13n_2/d3/gclk15 io_l13n_2/d3/gclk15 io_l13n_2/d3/gclk15 v9 dual/gclk 2 io_l13p_2/d4/gclk14 io_l13p_2/d4/gclk14 io_l13p_2/d4/gclk14 u9 dual/gclk 2 io_l15n_2/d1/gclk3 io_l15n_2/d1/gclk3 io_l15n_2/d1/gclk3 p10 dual/gclk 2 io_l15p_2/d2/gclk2 io_l15p_2/d2/gclk2 io_l15p_2/d2/gclk2 r10 dual/gclk 2 io_l16n_2/din/d0 io_l16n_2/din/d0 io_l16n_2/din/d0 n10 dual 2 io_l16p_2/m0 io_l16p_2/m0 io_l16p_2/m0 m10 dual 2 io_l18n_2 io_l18n_2 io_l18n_2 n11 i/o 2 io_l18p_2 io_l18p_2 io_l18p_2 p11 i/o 2 io_l19n_2/vref_2 io_l19n_2/vref_2 io_l19n_2/vref_2 v13 vref 2 io_l19p_2 io_l19p_2 io_l19p_2 v12 i/o 2 io_l20n_2 io_l20n_2 io_l20n_2 r12 i/o 2 io_l20p_2 io_l20p_2 io_l20p_2 t12 i/o 2 n.c. ( ) io_l21n_2 io_l21n_2 p12 500e: n.c. 1200e: i/o 1600e: i/o 2 n.c. ( ) io_l21p_2 io_l21p_2 n12 500e: n.c. 1200e: i/o 1600e: i/o 2 io_l22n_2/a22 io_l22n_2/a22 io_l22n_2/a22 r13 dual 2 io_l22p_2/a23 io_l22p_2/a23 io_l22p_2/a23 p13 dual 2 io_l24n_2/a20 io_l24n_2/a20 io_l24n_2/a20 r14 dual 2 io_l24p_2/a21 io_l24p_2/a21 io_l24p_2/a21 t14 dual 2 io_l25n_2/vs1/a18 io_l25n_2/vs1/a18 io_l25n_2/vs1/a18 u15 dual 2 io_l25p_2/vs2/a19 io_l25p_2/vs2/a19 io_l25p_2/vs2/a19 v15 dual 2 io_l26n_2/cclk io_l26n_2/cclk io_l26n_2/cclk u16 dual 2 io_l26p_2/vs0/a17 io_l26p_2/vs0/a17 io_l26p_2/vs0/a17 t16 dual 2 ip ip ip v2 input 2 ip ip ip v16 input 2 ip_l02n_2 ip_l02n_2 ip_l02n_2 v3 input 2 ip_l02p_2 ip_l02p_2 ip_l02p_2 v4 input 2 ip_l08n_2 ip_l08n_2 ip_l08n_2 r7 input 2 ip_l08p_2 ip_l08p_2 ip_l08p_2 t7 input 2 ip_l11n_2/vref_2 ip_l11n_2/vref_2 ip_l11n_2/vref_2 v8 vref 2 ip_l11p_2 ip_l11p_2 ip_l11p_2 u8 input 2 ip_l14n_2/m2/gclk1 ip_l14n_2/m2/gclk1 ip_l14n_2/m2/gclk1 t10 dual/gclk table 148: fg320 package pinout (continued) bank xc3s500e pin name xc3s1200e pin name xc3s1600e pin name fg320 ball type pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 209 product specification r 2 ip_l14p_2/rdwr_b/ gclk0 ip_l14p_2/rdwr_b/ gclk0 ip_l14p_2/rdwr_b/ gclk0 u10 dual/gclk 2 ip_l17n_2 ip_l17n_2 ip_l17n_2 u11 input 2 ip_l17p_2 ip_l17p_2 ip_l17p_2 t11 input 2 ip_l23n_2 ip_l23n_2 ip_l23n_2 u14 input 2 ip_l23p_2 ip_l23p_2 ip_l23p_2 v14 input 2 vcco_2 vcco_2 vcco_2 m8 vcco 2 vcco_2 vcco_2 vcco_2 m11 vcco 2 vcco_2 vcco_2 vcco_2 t6 vcco 2 vcco_2 vcco_2 vcco_2 t13 vcco 2 vcco_2 vcco_2 vcco_2 v10 vcco 3 n.c. ( ) io io d4 500e: n.c. 1200e: i/o 1600e: i/o 3 io_l01n_3 io_l01n_3 io_l01n_3 c2 i/o 3 io_l01p_3 io_l01p_3 io_l01p_3 c1 i/o 3 io_l02n_3/vref_3 io_l02n_3/vref_3 io_l02n_3/vref_3 d2 vref 3 io_l02p_3 io_l02p_3 io_l02p_3 d1 i/o 3 io_l03n_3 io_l03n_3 io_l03n_3 e1 i/o 3 io_l03p_3 io_l03p_3 io_l03p_3 e2 i/o 3 n.c. ( ) io_l04n_3 io_l04n_3 e3 500e: n.c. 1200e: i/o 1600e: i/o 3 n.c. ( ) io_l04p_3 io_l04p_3 e4 500e: n.c. 1200e: i/o 1600e: i/o 3 io_l05n_3 io_l05n_3 io_l05n_3 f2 i/o 3 io_l05p_3 io_l05p_3 io_l05p_3 f1 i/o 3 io_l06n_3/vref_3 io_l06n_3/vref_3 io_l06n_3/vref_3 g4 vref 3 io_l06p_3 io_l06p_3 io_l06p_3 g3 i/o 3 io_l07n_3 io_l07n_3 io_l07n_3 g5 i/o 3 io_l07p_3 io_l07p_3 io_l07p_3 g6 i/o 3 io_l08n_3 io_l08n_3 io_l08n_3 h5 i/o 3 io_l08p_3 io_l08p_3 io_l08p_3 h6 i/o 3 io_l09n_3 io_l09n_3 io_l09n_3 h3 i/o 3 io_l09p_3 io_l09p_3 io_l09p_3 h4 i/o 3 io_l10n_3 io_l10n_3 io_l10n_3 h1 i/o 3 io_l10p_3 io_l10p_3 io_l10p_3 h2 i/o 3 io_l11n_3/lhclk1 io_l11n_3/lhclk1 io_l11n_3/lhclk1 j4 lhclk 3 io_l11p_3/lhclk0 io_l11p_3/lhclk0 io_l11p_3/lhclk0 j5 lhclk 3 io_l12n_3/lhclk3/ irdy2 io_l12n_3/lhclk3/ irdy2 io_l12n_3/lhclk3/ irdy2 j2 lhclk table 148: fg320 package pinout (continued) bank xc3s500e pin name xc3s1200e pin name xc3s1600e pin name fg320 ball type pinout descriptions 210 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r 3 io_l12p_3/lhclk2 io_l12p_3/lhclk2 io_l12p_3/lhclk2 j1 lhclk 3 io_l13n_3/lhclk5 io_l13n_3/lhclk5 io_l13n_3/lhclk5 k4 lhclk 3 io_l13p_3/lhclk4/ trdy2 io_l13p_3/lhclk4/ trdy2 io_l13p_3/lhclk4/ trdy2 k3 lhclk 3 io_l14n_3/lhclk7 io_l14n_3/lhclk7 io_l14n_3/lhclk7 k5 lhclk 3 io_l14p_3/lhclk6 io_l14p_3/lhclk6 io_l14p_3/lhclk6 k6 lhclk 3 io_l15n_3 io_l15n_3 io_l15n_3 l2 i/o 3 io_l15p_3 io_l15p_3 io_l15p_3 l1 i/o 3 io_l16n_3 io_l16n_3 io_l16n_3 l4 i/o 3 io_l16p_3 io_l16p_3 io_l16p_3 l3 i/o 3 io_l17n_3/vref_3 io_l17n_3/vref_3 io_l17n_3/vref_3 l5 vref 3 io_l17p_3 io_l17p_3 io_l17p_3 l6 i/o 3 io_l18n_3 io_l18n_3 io_l18n_3 m3 i/o 3 io_l18p_3 io_l18p_3 io_l18p_3 m4 i/o 3 io_l19n_3 io_l19n_3 io_l19n_3 m6 i/o 3 io_l19p_3 io_l19p_3 io_l19p_3 m5 i/o 3 io_l20n_3 io_l20n_3 io_l20n_3 n5 i/o 3 io_l20p_3 io_l20p_3 io_l20p_3 n4 i/o 3 io_l21n_3 io_l21n_3 io_l21n_3 p1 i/o 3 io_l21p_3 io_l21p_3 io_l21p_3 p2 i/o 3 n.c. ( ) io_l22n_3 io_l22n_3 p4 500e: n.c. 1200e: i/o 1600e: i/o 3 n.c. ( ) io_l22p_3 io_l22p_3 p3 500e: n.c. 1200e: i/o 1600e: i/o 3 io_l23n_3 io_l23n_3 io_l23n_3 r2 i/o 3 io_l23p_3 io_l23p_3 io_l23p_3 r3 i/o 3 io_l24n_3 io_l24n_3 io_l24n_3 t1 i/o 3 io_l24p_3 io_l24p_3 io_l24p_3 t2 i/o 3 ip ip ip d3 input 3 io ip ip f4 500e: i/o 1200e: input 1600e: input 3 ip ip ip f5 input 3 ip ip ip g1 input 3 ip ip ip j7 input 3 ip ip ip k2 input 3 ip ip ip k7 input 3 ip ip ip m1 input 3 ip ip ip n1 input 3 ip ip ip n2 input table 148: fg320 package pinout (continued) bank xc3s500e pin name xc3s1200e pin name xc3s1600e pin name fg320 ball type pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 211 product specification r 3 ip ip ip r1 input 3 ip ip ip u1 input 3 ip/vref_3 ip/vref_3 ip/vref_3 j6 vref 3 io/vref_3 ip/vref_3 ip/vref_3 r4 500e: vref(i/o) 1200e: vref(input) 1600e: vref(input) 3 vcco_3 vcco_3 vcco_3 f3 vcco 3 vcco_3 vcco_3 vcco_3 h7 vcco 3 vcco_3 vcco_3 vcco_3 k1 vcco 3 vcco_3 vcco_3 vcco_3 l7 vcco 3 vcco_3 vcco_3 vcco_3 n3 vcco gnd gnd gnd gnd a1 gnd gnd gnd gnd gnd a18 gnd gnd gnd gnd gnd b2 gnd gnd gnd gnd gnd b17 gnd gnd gnd gnd gnd c10 gnd gnd gnd gnd gnd g7 gnd gnd gnd gnd gnd g12 gnd gnd gnd gnd gnd h8 gnd gnd gnd gnd gnd h9 gnd gnd gnd gnd gnd h10 gnd gnd gnd gnd gnd h11 gnd gnd gnd gnd gnd j3 gnd gnd gnd gnd gnd j8 gnd gnd gnd gnd gnd j11 gnd gnd gnd gnd gnd k8 gnd gnd gnd gnd gnd k11 gnd gnd gnd gnd gnd k16 gnd gnd gnd gnd gnd l8 gnd gnd gnd gnd gnd l9 gnd gnd gnd gnd gnd l10 gnd gnd gnd gnd gnd l11 gnd gnd gnd gnd gnd m7 gnd gnd gnd gnd gnd m12 gnd gnd gnd gnd gnd t9 gnd gnd gnd gnd gnd u2 gnd gnd gnd gnd gnd u17 gnd gnd gnd gnd gnd v1 gnd gnd gnd gnd gnd v18 gnd vccaux done done done v17 config table 148: fg320 package pinout (continued) bank xc3s500e pin name xc3s1200e pin name xc3s1600e pin name fg320 ball type pinout descriptions 212 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r vccaux prog_b prog_b prog_b b1 config vccaux tck tck tck a17 jtag vccaux tdi tdi tdi a2 jtag vccaux tdo tdo tdo c16 jtag vccaux tms tms tms d15 jtag vccaux vccaux vccaux vccaux b7 vccaux vccaux vccaux vccaux vccaux b12 vccaux vccaux vccaux vccaux vccaux g2 vccaux vccaux vccaux vccaux vccaux g17 vccaux vccaux vccaux vccaux vccaux m2 vccaux vccaux vccaux vccaux vccaux m17 vccaux vccaux vccaux vccaux vccaux u7 vccaux vccaux vccaux vccaux vccaux u12 vccaux vccint vccint vccint vccint e5 vccint vccint vccint vccint vccint e14 vccint vccint vccint vccint vccint f6 vccint vccint vccint vccint vccint f13 vccint vccint vccint vccint vccint n6 vccint vccint vccint vccint vccint n13 vccint vccint vccint vccint vccint p5 vccint vccint vccint vccint vccint p14 vccint table 148: fg320 package pinout (continued) bank xc3s500e pin name xc3s1200e pin name xc3s1600e pin name fg320 ball type pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 213 product specification r user i/os by bank table 149 and ta bl e 1 5 0 indicate how the available user-i/o pins are distributed between the four i/o banks on the fg320 package. table 149: user i/os per bank for xc3s500e in the fg320 package package edge i/o bank maximum i/o all possible i/o pins by type i/o input dual vref (1) clk (1) to p 0 58 29 14 1 6 8 right 1 58 22 10 21 5 0 (2) bottom 2 58 17 13 24 4 0 (2) left 3 58 34 11 0 5 8 total 232 102 48 46 20 16 notes: 1. some vref and clk pins are on input pins. 2. the eight global clock pins in this bank have optional functionality during configuration and are counted in the dual column. table 150: user i/os per bank for xc3s1200e and xc3s1600e in the fg320 package package edge i/o bank maximum i/o all possible i/o pins by type i/o input dual vref (1) clk (1) to p 0 61 34 12 1 6 8 right 1 63 25 12 21 5 0 (2) bottom 2 63 23 11 24 5 0 (2) left 3 63 38 12 0 5 8 total 250 120 47 46 21 16 notes: 1. some vref and clk pins are on input pins. 2. the eight global clock pins in this bank have optional functionality during configuration and are counted in the dual column. pinout descriptions 214 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r footprint migration differences table 151 summarizes any footprint and functionality differ- ences between the xc3s500e, the xc3s1200e, and the xc3s1600e fpgas that may affect easy migration between devices available in the fg320 package. there are 26 such balls. all other pins not listed in ta b l e 1 5 1 uncondi- tionally migrate between spartan-3e devices available in the fg320 package. the xc3s500e is duplicated on both the left and right sides of the table to show migrations to and from the xc3s1200e and the xc3s1600e. the arrows indicate the direction for easy migration. a double-ended arrow ( ) indicates that the two pins have identical functionality. a left-facing arrow ( ) indicates that the pin on the device on the right uncon- ditionally migrates to the pin on the device on the left. it may be possible to migrate the opposite direction depending on the i/o configuration. for example, an i/o pin (type = i/o) can migrate to an input-only pin (type = input) if the i/o pin is configured as an input. table 151: fg320 footprint migration differences pin bank xc3s500e migration xc3s1200e migration xc3s1600e migration xc3s500e a7 0 input i/o i/o input a12 0 n.c. i/o i/o n.c. d4 3 n.c. i/o i/o n.c. d6 0 n.c. i/o i/o n.c. d13 0 input i/o i/o input e3 3 n.c. i/o i/o n.c. e4 3 n.c. i/o i/o n.c. e6 0 n.c. i/o i/o n.c. e15 1 n.c. i/o i/o n.c. e16 1 n.c. i/o i/o n.c. e17 1 i/o input input i/o f4 3 i/o input input i/o n12 2 n.c. i/o i/o n.c. n14 1 n.c. i/o i/o n.c. n15 1 n.c. i/o i/o n.c. p3 3 n.c. i/o i/o n.c. p4 3 n.c. i/o i/o n.c. p12 2 n.c. i/o i/o n.c. p15 1 i/o input input i/o p16 1 n.c. i/o i/o n.c. r4 3 vref(i/o) vref(input) vref(input) vref(i/o) u6 2 input i/o i/o input u13 2 input i/o i/o input v5 2 n.c. i/o i/o n.c. v6 2 n.c. vref vref n.c. v7 2 n.c. i/o i/o n.c. differences 26 0 26 legend: this pin is identical on the device on the left and the right. this pin can unconditionally migr ate from the device on the left to the device on the right. migration in the other direction m ay be possible depending on how the pin is configured for the device on the right. this pin can unconditionally migr ate from the device on the right to the device on the left. migration in the other direction m ay be possible depending on how the pin is configured for the device on the left. pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 215 product specification r fg320 footprint figure 87: fg320 package footprint (top view) 123456789101112131415161718 a gnd tdi input i/o l24p_0 input l22p_0 i/o l20n_0 input ? ? i/o vcco_0 i/o l12n_0 gclk7 i/o i/o l05p_0 i/o l04n_0 input l02n_0 i/o l01n_0 tck gnd b prog_b gnd i/o l25n_0 hswap i/o l24n_0 input l22n_0 i/o l20p_0 vccaux input l13p_0 gclk8 input l13n_0 gclk9 i/o l12p_0 gclk6 i/o vref_0 vccaux i/o l05n_0 vref_0 i/o l04p_0 input l02p_0 i/o l01p_0 gnd input c i/o l01p_3 i/o l01n_3 i/o l25p_0 i/o i/o l23p_0 vcco_0 i/o l18p_0 input l16p_0 i/o l14p_0 gclk10 gnd i/o l09p_0 input l07p_0 vcco_0 i/o l03n_0 vref_0 input tdo i/o l24n_1 ldc2 i/o l24p_1 ldc1 d i/o l02p_3 i/o l02n_3 vref_3 input i/o ? i/o l23n_0 vref_0 i/o l21p_0 ? i/o l18n_0 vref_0 input l16n_0 i/o l14n_0 gclk11 i/o l11p_0 gclk4 i/o l09n_0 input l07n_0 input ? ? ? ? ? ? ? ? i/o l03p_0 tm s i/o l23n_1 ldc0 i/o l23p_1 hdc input vref_1 e i/o l03n_3 i/o l03p_3 i/o l04n_3 ? i/o l04p_3 ? vccint i/o l21n_0 ? i/o l19n_0 vref_0 i/o l17p_0 i/o l15p_0 i/o l11n_0 gclk5 i/o l08p_0 i/o l06n_0 i/o vccint i/o l22p_1 ? i/o l22n_1 ? input ? ? ? ? ? ? ? ? input f i/o l05p_3 i/o l05n_3 vcco_3 input ? ? ? ? ? ? ? ? input vccint i/o l19p_0 i/o l17n_0 i/o l15n_0 input l10p_0 i/o l08n_0 i/o l06p_0 vccint i/o l21n_1 i/o l21p_1 vcco_1 i/o l19n_1 i/o l19p_1 g input vccaux i/o l06p_3 i/o l06n_3 vref_3 i/o l07n_3 i/o l07p_3 gnd vcco_0 i/o input l10n_0 vcco_0 gnd i/o l20n_1 i/o l20p_1 i/o l18p_1 i/o l18n_1 vccaux input h i/o l10n_3 i/o l10p_3 i/o l09n_3 i/o l09p_3 i/o l08n_3 i/o l08p_3 vcco_3 gnd gnd gnd gnd vcco_1 input i/o l17p_1 i/o l17n_1 i/o l16p_1 i/o l16n_1 a0 input vref_1 j i/o l12p_3 lhclk2 i/o l12n_3 lhclk3 irdy2 gnd i/o l11n_3 lhclk1 i/o l11p_3 lhclk0 input vref_3 input gnd gnd i/o l15p_1 a2 i/o l15n_1 a1 4 _1 vcco_1 k vcco_3 input i/o l13p_3 lhclk4 t rdy2 i/o l13n_3 lhclk5 i/o l14n_3 lhclk7 i/o l14p_3 lhclk6 input gnd gnd gnd input input l i/o l15p_3 i/o l15n_3 i/o l16p_3 i/o l16n_3 i/o l17n_3 vref_3 i/o l17p_3 vcco_3 gnd gnd gnd gnd vcco_1 input input i/o l09n_1 a11 i/o l09p_1 a12 i/o l10n_1 vref_1 i/o l10p_1 m input vccaux i/o l18n_3 i/o l18p_3 i/o l19p_3 i/o l19n_3 gnd vcco_2 i/o l16p_2 m0 vcco_2 gnd i/o l05n_1 vref_1 i/o l05p_1 i/o l07p_1 i/o l07n_1 vccaux i/o l08n_1 n input input vcco_3 i/o l20p_3 i/o l20n_3 vccint i/o l07p_2 i/o l09n_2 i/o i/o l16n_2 din d0 i/o l18n_2 i/o l21p_2 ? vccint i/o l04n_1 ? i/o l04p_1 ? vcco_1 input i/o l08p_1 p i/o l21n_3 i/o l21p_3 i/o l22p_3 ? i/o l22n_3 ? vccint i/o l05n_2 i/o l07n_2 i/o l09p_2 i/o i/o l18p_2 i/o l21n_2 ? i/o l22p_2 a23 vccint input ? ? ? ? ? ? ? ? i/o ? i/o l06p_1 i/o l06n_1 r input i/o l23n_3 i/o l23p_3 input vref_3 ? ? i/o l04p_2 i/o l05p_2 input l08n_2 i/o l10p_2 i/o d5 i/o i/o l20n_2 i/o l22n_2 a22 i/o l24n_2 a20 i/o l03p_1 i/o l03n_1 vref_1 input i/o l02p_1 a14 t i/o l24n_3 i/o l24p_3 i/o l01n_2 init_b i/o l03n_2 mosi csi_b i/o l04n_2 vcco_2 input l08p_2 i/o l10n_2 gnd input l17p_2 i/o l20p_2 vcco_2 i/o l24p_2 a21 i/o vref_2 i/o l26p_2 v s0 a 17 i/o l01n_1 a15 i/o l02n_1 a13 u input gnd i/o l01p_2 cso_b i/o l03p_2 dout busy i/o vref_2 input ? ? ? ? ? ? ? ? vccaux input l11p_2 input l17n_2 vccaux input ? ? ? ? ? ? ? ? input l23n_2 i/o l25n_2 vs1 a 18 i/o l26n_2 cclk gnd i/o l01p_1 a16 v gnd input input l02n_2 input l02p_2 i/o l06p_2 ? i/o l06n_2 vref_2 ? i/o ? input l11n_2 vref_2 vcco_2 i/o m1 i/o l19p_2 i/o l19n_2 vref_2 input l23p_2 i/o l25p_2 vs2 a19 input done gnd bank 0 bank 3 bank 1 bank 2 i/o l14n_1 a3 rhclk7 rhclk6 l14p_1 a 4 i/o l13n_1 a5 rhclk5 i/o i/o l13p a 6 rhclk4 irdy1 l11n_1 a9 rhclk1 i/o i/o l11p_1 rhclk0 a10 trdy1 rhclk3 a 7 l12n_1 i/o i/o l12p_1 rhclk2 a 8 i/o l12n_2 d6 gclk13 gclk12 d7 l12p_2 gclk3 d1 l15n_2 i/o gclk2 d2 l15p_2 i/o gclk1 m2 l14n_2 input gclk0 l14p_2 rdwr_b input gclk14 d4 l13p_2 i/o gclk15 d3 l13n_2 i/o DS312-4_06_022106 i/o ? 102- 120 i/o: unrestricted, general-purpose user i/o 46 dual: configuration pin, then possible user-i/o 20- 21 vref: user i/o or input voltage reference for bank 47- 48 input: unrestricted, general-purpose input pin 16 clk: user i/o, input, or global buffer input 20 vcco: output voltage supply for bank 2 config: dedicated configuration pins 4 jtag: dedicated jtag port pins 8 vccint: internal core supply voltage (+1.2v) 18 n.c.: not connected. only the xc3s500e has these pins ( ). 28 gnd: ground 8 vccaux: auxiliary supply voltage (+2.5v) pinout descriptions 216 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r fg400: 400-ball fine-p itch ball grid array the 400-ball fine-pitch ball grid array, fg400, supports two different spartan-3e fpgas, including the xc3s1200e and the xc3s1600e. both devices share a common footprint for this package as shown in ta bl e 1 5 2 and figure 88 . table 152 lists all the fg400 package pins. they are sorted by bank number and then by pin name. pairs of pins that form a differential i/o pair appear together in the table. the table also shows the pin number for each pin and the pin type, as defined earlier. an electronic version of this package pinout table and foot- print diagram is available for download from the xilinx web- site at: http://www.xilinx.com/support/doc umentation/data_sheets/s3e_pin.zip pinout table table 152: fg400 package pinout bank xc3s1200e xc3s1600e pin name fg400 ball type 0 io a3 i/o 0 io a8 i/o 0 io a12 i/o 0 io c7 i/o 0 io c10 i/o 0 io e8 i/o 0 io e13 i/o 0 io e16 i/o 0 io f13 i/o 0 io f14 i/o 0 io g7 i/o 0io/vref_0 c11vref 0 io_l01n_0 b17 i/o 0 io_l01p_0 c17 i/o 0 io_l03n_0/vref_0 a18 vref 0 io_l03p_0 a19 i/o 0 io_l04n_0 a17 i/o 0 io_l04p_0 a16 i/o 0 io_l06n_0 a15 i/o 0 io_l06p_0 b15 i/o 0 io_l07n_0 c14 i/o 0 io_l07p_0 d14 i/o 0 io_l09n_0/vref_0 a13 vref 0 io_l09p_0 a14 i/o 0 io_l10n_0 b13 i/o 0 io_l10p_0 c13 i/o 0 io_l12n_0 c12 i/o 0 io_l12p_0 d12 i/o 0 io_l13n_0 e12 i/o 0 io_l13p_0 f12 i/o 0 io_l15n_0/gclk5 g11 gclk 0 io_l15p_0/gclk4 f11 gclk 0 io_l16n_0/gclk7 e10 gclk 0 io_l16p_0/gclk6 e11 gclk 0 io_l18n_0/gclk11 a9 gclk 0 io_l18p_0/gclk10 a10 gclk 0 io_l19n_0 f9 i/o 0 io_l19p_0 e9 i/o 0 io_l21n_0 c9 i/o 0 io_l21p_0 d9 i/o 0 io_l22n_0/vref_0 b8 vref 0 io_l22p_0 b9 i/o 0 io_l24n_0/vref_0 f7 vref 0 io_l24p_0 f8 i/o 0 io_l25n_0 a6 i/o 0 io_l25p_0 a7 i/o 0 io_l27n_0 b5 i/o 0 io_l27p_0 b6 i/o 0 io_l28n_0 d6 i/o 0 io_l28p_0 c6 i/o 0 io_l30n_0/vref_0 c5 vref 0 io_l30p_0 d5 i/o 0 io_l31n_0 a2 i/o 0 io_l31p_0 b2 i/o 0 io_l32n_0/hswap d4 dual 0 io_l32p_0 c4 i/o 0ip b18input 0ip e5input 0 ip_l02n_0 c16 input 0 ip_l02p_0 d16 input 0 ip_l05n_0 d15 input 0 ip_l05p_0 c15 input 0 ip_l08n_0 e14 input 0 ip_l08p_0 e15 input 0 ip_l11n_0 g14 input table 152: fg400 package pinout (continued) bank xc3s1200e xc3s1600e pin name fg400 ball type pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 217 product specification r 0 ip_l11p_0 g13 input 0 ip_l14n_0 b11 input 0 ip_l14p_0 b12 input 0 ip_l17n_0/gclk9 g10 gclk 0 ip_l17p_0/gclk8 h10 gclk 0 ip_l20n_0 g9 input 0 ip_l20p_0 g8 input 0 ip_l23n_0 c8 input 0 ip_l23p_0 d8 input 0 ip_l26n_0 e6 input 0 ip_l26p_0 e7 input 0 ip_l29n_0 a4 input 0 ip_l29p_0 a5 input 0 vcco_0 b4 vcco 0 vcco_0 b10 vcco 0 vcco_0 b16 vcco 0 vcco_0 d7 vcco 0 vcco_0 d13 vcco 0 vcco_0 f10 vcco 1 io_l01n_1/a15 u18 dual 1 io_l01p_1/a16 u17 dual 1 io_l02n_1/a13 t18 dual 1 io_l02p_1/a14 t17 dual 1 io_l03n_1/vref_1 v19 vref 1 io_l03p_1 u19 i/o 1 io_l04n_1 w20 i/o 1 io_l04p_1 v20 i/o 1 io_l05n_1 r18 i/o 1 io_l05p_1 r17 i/o 1 io_l06n_1 t20 i/o 1 io_l06p_1 u20 i/o 1 io_l07n_1 p18 i/o 1 io_l07p_1 p17 i/o 1 io_l08n_1/vref_1 p20 vref 1 io_l08p_1 r20 i/o 1 io_l09n_1 p16 i/o 1 io_l09p_1 n16 i/o 1 io_l10n_1 n19 i/o 1 io_l10p_1 n18 i/o 1 io_l11n_1 n15 i/o table 152: fg400 package pinout (continued) bank xc3s1200e xc3s1600e pin name fg400 ball type 1 io_l11p_1 m15 i/o 1 io_l12n_1/a11 m18 dual 1 io_l12p_1/a12 m17 dual 1 io_l13n_1/vref_1 l19 vref 1 io_l13p_1 m19 i/o 1 io_l14n_1/a9/rhclk1 l16 rhclk/ dual 1 io_l14p_1/a10/rhclk0 m16 rhclk/ dual 1 io_l15n_1/a7/rhclk3/ trdy1 l14 rhclk/ dual 1 io_l15p_1/a8/rhclk2 l15 rhclk/ dual 1 io_l16n_1/a5/rhclk5 k14 rhclk/ dual 1 io_l16p_1/a6/rhclk4/ irdy1 k13 rhclk/ dual 1 io_l17n_1/a3/rhclk7 j20 rhclk/ dual 1 io_l17p_1/a4/rhclk6 k20 rhclk/ dual 1 io_l18n_1/a1 k16 dual 1 io_l18p_1/a2 j16 dual 1 io_l19n_1/a0 j13 dual 1 io_l19p_1 j14 i/o 1 io_l20n_1 j17 i/o 1 io_l20p_1 j18 i/o 1 io_l21n_1 h19 i/o 1 io_l21p_1 j19 i/o 1 io_l22n_1 h15 i/o 1 io_l22p_1 h16 i/o 1 io_l23n_1 h18 i/o 1 io_l23p_1 h17 i/o 1 io_l24n_1/vref_1 h20 vref 1 io_l24p_1 g20 i/o 1 io_l25n_1 g16 i/o 1 io_l25p_1 f16 i/o 1 io_l26n_1 f19 i/o 1 io_l26p_1 f20 i/o 1 io_l27n_1 f18 i/o 1 io_l27p_1 f17 i/o 1 io_l28n_1 d20 i/o 1 io_l28p_1 e20 i/o table 152: fg400 package pinout (continued) bank xc3s1200e xc3s1600e pin name fg400 ball type pinout descriptions 218 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r 1 io_l29n_1/ldc0 d18 dual 1 io_l29p_1/hdc e18 dual 1 io_l30n_1/ldc2 c19 dual 1 io_l30p_1/ldc1 c20 dual 1ip b20input 1ip g15input 1ip g18input 1ip h14input 1ip j15input 1 ip l18 input 1ip m20input 1ip n14input 1ip n20input 1ip p15input 1ip r16input 1ip r19input 1 ip/vref_1 e19 vref 1 ip/vref_1 k18 vref 1 vcco_1 d19 vcco 1 vcco_1 g17 vcco 1 vcco_1 k15 vcco 1 vcco_1 k19 vcco 1 vcco_1 n17 vcco 1 vcco_1 t19 vcco 2 io p8 i/o 2 io p13 i/o 2 io r9 i/o 2 io r13 i/o 2 io w15 i/o 2 io y5 i/o 2 io y7 i/o 2 io y13 i/o 2io/d5 n11dual 2io/m1 t11dual 2 io/vref_2 y3 vref 2 io/vref_2 y17 vref 2 io_l01n_2/init_b v4 dual 2 io_l01p_2/cso_b u4 dual 2 io_l03n_2/mosi/csi_b v5 dual 2 io_l03p_2/dout/busy u5 dual table 152: fg400 package pinout (continued) bank xc3s1200e xc3s1600e pin name fg400 ball type 2 io_l04n_2 y4 i/o 2 io_l04p_2 w4 i/o 2 io_l06n_2 t6 i/o 2 io_l06p_2 t5 i/o 2 io_l07n_2 u7 i/o 2 io_l07p_2 v7 i/o 2 io_l09n_2/vref_2 r7 vref 2 io_l09p_2 t7 i/o 2 io_l10n_2 v8 i/o 2 io_l10p_2 w8 i/o 2 io_l12n_2 u9 i/o 2 io_l12p_2 v9 i/o 2 io_l13n_2 y8 i/o 2 io_l13p_2 y9 i/o 2 io_l15n_2/d6/gclk13 w10 dual/ gclk 2 io_l15p_2/d7/gclk12 w9 dual/ gclk 2 io_l16n_2/d3/gclk15 p10 dual/ gclk 2 io_l16p_2/d4/gclk14 r10 dual/ gclk 2 io_l18n_2/d1/gclk3 v11 dual/ gclk 2 io_l18p_2/d2/gclk2 v10 dual/ gclk 2 io_l19n_2/din/d0 y12 dual 2 io_l19p_2/m0 y11 dual 2 io_l21n_2 u12 i/o 2 io_l21p_2 v12 i/o 2 io_l22n_2/vref_2 w12 vref 2 io_l22p_2 w13 i/o 2 io_l24n_2 u13 i/o 2 io_l24p_2 v13 i/o 2 io_l25n_2 p14 i/o 2 io_l25p_2 r14 i/o 2 io_l27n_2/a22 y14 dual 2 io_l27p_2/a23 y15 dual 2 io_l28n_2 t15 i/o 2 io_l28p_2 u15 i/o 2 io_l30n_2/a20 v16 dual 2 io_l30p_2/a21 u16 dual table 152: fg400 package pinout (continued) bank xc3s1200e xc3s1600e pin name fg400 ball type pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 219 product specification r 2 io_l31n_2/vs1/a18 y18 dual 2 io_l31p_2/vs2/a19 w18 dual 2 io_l32n_2/cclk w19 dual 2 io_l32p_2/vs0/a17 y19 dual 2ip t16input 2 ip w3 input 2 ip_l02n_2 y2 input 2 ip_l02p_2 w2 input 2 ip_l05n_2 v6 input 2 ip_l05p_2 u6 input 2 ip_l08n_2 y6 input 2 ip_l08p_2 w6 input 2 ip_l11n_2 r8 input 2 ip_l11p_2 t8 input 2 ip_l14n_2/vref_2 t10 vref 2 ip_l14p_2 t9 input 2 ip_l17n_2/m2/gclk1 p12 dual/ gclk 2 ip_l17p_2/rdwr_b/ gclk0 p11 dual/ gclk 2 ip_l20n_2 t12 input 2 ip_l20p_2 r12 input 2 ip_l23n_2/vref_2 t13 vref 2 ip_l23p_2 t14 input 2 ip_l26n_2 v14 input 2 ip_l26p_2 v15 input 2 ip_l29n_2 w16 input 2 ip_l29p_2 y16 input 2 vcco_2 r11 vcco 2 vcco_2 u8 vcco 2 vcco_2 u14 vcco 2 vcco_2 w5 vcco 2 vcco_2 w11 vcco 2 vcco_2 w17 vcco 3 io_l01n_3 d2 i/o 3 io_l01p_3 d3 i/o 3 io_l02n_3/vref_3 e3 vref 3 io_l02p_3 e4 i/o 3 io_l03n_3 c1 i/o 3 io_l03p_3 b1 i/o 3 io_l04n_3 e1 i/o table 152: fg400 package pinout (continued) bank xc3s1200e xc3s1600e pin name fg400 ball type 3 io_l04p_3 d1 i/o 3 io_l05n_3 f3 i/o 3 io_l05p_3 f4 i/o 3 io_l06n_3 f1 i/o 3 io_l06p_3 f2 i/o 3 io_l07n_3 g4 i/o 3 io_l07p_3 g3 i/o 3 io_l08n_3 g5 i/o 3 io_l08p_3 h5 i/o 3 io_l09n_3/vref_3 h3 vref 3 io_l09p_3 h2 i/o 3 io_l10n_3 h7 i/o 3 io_l10p_3 h6 i/o 3 io_l11n_3 j4 i/o 3 io_l11p_3 j3 i/o 3 io_l12n_3 j1 i/o 3 io_l12p_3 j2 i/o 3 io_l13n_3 j6 i/o 3 io_l13p_3 k6 i/o 3 io_l14n_3/lhclk1 k2 lhclk 3 io_l14p_3/lhclk0 k3 lhclk 3 io_l15n_3/lhclk3/irdy2 l7 lhclk 3 io_l15p_3/lhclk2 k7 lhclk 3 io_l16n_3/lhclk5 l1 lhclk 3 io_l16p_3/lhclk4/trdy2 m1 lhclk 3 io_l17n_3/lhclk7 l3 lhclk 3 io_l17p_3/lhclk6 m3 lhclk 3 io_l18n_3 m7 i/o 3 io_l18p_3 m8 i/o 3 io_l19n_3 m4 i/o 3 io_l19p_3 m5 i/o 3 io_l20n_3/vref_3 n6 vref 3 io_l20p_3 m6 i/o 3 io_l21n_3 n2 i/o 3 io_l21p_3 n1 i/o 3 io_l22n_3 p7 i/o 3 io_l22p_3 n7 i/o 3 io_l23n_3 n4 i/o 3 io_l23p_3 n3 i/o 3 io_l24n_3 r1 i/o table 152: fg400 package pinout (continued) bank xc3s1200e xc3s1600e pin name fg400 ball type pinout descriptions 220 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r 3 io_l24p_3 p1 i/o 3 io_l25n_3 r5 i/o 3 io_l25p_3 p5 i/o 3 io_l26n_3 t2 i/o 3 io_l26p_3 r2 i/o 3 io_l27n_3 r4 i/o 3 io_l27p_3 r3 i/o 3 io_l28n_3/vref_3 t1 vref 3 io_l28p_3 u1 i/o 3 io_l29n_3 t3 i/o 3 io_l29p_3 u3 i/o 3 io_l30n_3 v1 i/o 3 io_l30p_3 v2 i/o 3 ip f5 input 3 ip g1 input 3 ip g6 input 3 ip h1 input 3 ip j5 input 3 ip l5 input 3 ip l8 input 3 ip m2 input 3 ip n5 input 3 ip p3 input 3 ip t4 input 3 ip w1 input 3 ip/vref_3 k5 vref 3 ip/vref_3 p6 vref 3 vcco_3 e2 vcco 3 vcco_3 h4 vcco 3 vcco_3 l2 vcco 3 vcco_3 l6 vcco 3 vcco_3 p4 vcco 3 vcco_3 u2 vcco gnd gnd a1 gnd gnd gnd a11 gnd gnd gnd a20 gnd gnd gnd b7 gnd gnd gnd b14 gnd gnd gnd c3 gnd gnd gnd c18 gnd table 152: fg400 package pinout (continued) bank xc3s1200e xc3s1600e pin name fg400 ball type gnd gnd d10 gnd gnd gnd f6 gnd gnd gnd f15 gnd gnd gnd g2 gnd gnd gnd g12 gnd gnd gnd g19 gnd gnd gnd h8 gnd gnd gnd j9 gnd gnd gnd j11 gnd gnd gnd k1 gnd gnd gnd k8 gnd gnd gnd k10 gnd gnd gnd k12 gnd gnd gnd k17 gnd gnd gnd l4 gnd gnd gnd l9 gnd gnd gnd l11 gnd gnd gnd l13 gnd gnd gnd l20 gnd gnd gnd m10 gnd gnd gnd m12 gnd gnd gnd n13 gnd gnd gnd p2 gnd gnd gnd p9 gnd gnd gnd p19 gnd gnd gnd r6 gnd gnd gnd r15 gnd gnd gnd u11 gnd gnd gnd v3 gnd gnd gnd v18 gnd gnd gnd w7 gnd gnd gnd w14 gnd gnd gnd y1 gnd gnd gnd y10 gnd gnd gnd y20 gnd vccaux done v17 config vccaux prog_b c2 config vccaux tck d17 jtag vccaux tdi b3 jtag vccaux tdo b19 jtag table 152: fg400 package pinout (continued) bank xc3s1200e xc3s1600e pin name fg400 ball type pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 221 product specification r user i/os by bank table 153 indicates how the 304 available user-i/o pins are distributed between the four i/o banks on the fg400 pack- age. footprint migration differences the xc3s1200e and xc3s1600e fpgas have identical footprints in the fg400 package. designs can migrate between the xc3s1200e and xc3s1600e fpgas without further consideration. vccaux tms e17 jtag vccaux vccaux d11 vccaux vccaux vccaux h12 vccaux vccaux vccaux j7 vccaux vccaux vccaux k4 vccaux vccaux vccaux l17 vccaux vccaux vccaux m14 vccaux vccaux vccaux n9 vccaux vccaux vccaux u10 vccaux vccint vccint h9 vccint vccint vccint h11 vccint vccint vccint h13 vccint vccint vccint j8 vccint vccint vccint j10 vccint table 152: fg400 package pinout (continued) bank xc3s1200e xc3s1600e pin name fg400 ball type vccint vccint j12 vccint vccint vccint k9 vccint vccint vccint k11 vccint vccint vccint l10 vccint vccint vccint l12 vccint vccint vccint m9 vccint vccint vccint m11 vccint vccint vccint m13 vccint vccint vccint n8 vccint vccint vccint n10 vccint vccint vccint n12 vccint table 152: fg400 package pinout (continued) bank xc3s1200e xc3s1600e pin name fg400 ball type table 153: user i/os per bank for the xc3s1200e and xc3s1600e in the fg400 package package edge i/o bank maximum i/o all possible i/o pins by type i/o input dual vref (1) clk (1) to p 0 78 43 20 1 6 8 right 1 74 35 12 21 6 0 (2) bottom 2 78 30 18 24 6 0 (2) left 3 74 48 12 0 6 8 total 304 156 62 46 24 16 notes: 1. some vref and clk pins are on input pins. 2. the eight global clock pins in this bank have optional functionality during configuration and are counted in the dual column. pinout descriptions 222 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r fg400 footprint left half of package (top view) 156 i/o: unrestricted, general-purpose user i/o 62 input: unrestricted, general-purpose input pin 46 dual: configuration pin, then possible user i/o 24 vref: user i/o or input voltage reference for bank 16 clk: user i/o, input, or clock buffer input 2 config: dedicated configuration pins 4 jtag: dedicated jtag port pins 42 gnd: ground 24 vcco: output voltage supply for bank 16 vccint: internal core supply voltage (+1.2v) 8 vccaux: auxiliary supply voltage (+2.5v) 0 n.c.: not connected figure 88: fg400 package footprint (top view) 12345678 10 a gnd i/o l31n_0 i/o input l29n_0 input l29p_0 i/o l25n_0 i/o l25p_0 i/o i/o l18n_0 gclk11 i/o l18p_0 gclk10 b i/o l03p_3 i/o l31p_0 tdi vcco_0 i/o l27n_0 i/o l27p_0 gnd i/o l22n_0 vref_0 i/o l22p_0 vcco_0 c i/o l03n_3 prog_b gnd i/o l32p_0 i/o l30n_0 vref_0 i/o l28p_0 i/o input l23n_0 i/o l21n_0 i/o d i/o l04p_3 i/o l01n_3 i/o l01p_3 i/o l32n_0 hswap i/o l30p_0 i/o l28n_0 vcco_0 input l23p_0 i/o l21p_0 gnd e i/o l04n_3 vcco_3 i/o l02n_3 vref_3 i/o l02p_3 input input l26n_0 input l26p_0 i/o i/o l19p_0 i/o l16n_0 gclk7 f i/o l06n_3 i/o l06p_3 i/o l05n_3 i/o l05p_3 input gnd i/o l24n_0 vref_0 i/o l24p_0 i/o l19n_0 vcco_0 g input gnd i/o l07p_3 i/o l07n_3 i/o l08n_3 input i/o input l20p_0 input l20n_0 input l17n_0 gclk9 h input i/o l09p_3 i/o l09n_3 vref_3 vcco_3 i/o l08p_3 i/o l10p_3 i/o l10n_3 gnd vccint input l17p_0 gclk8 j i/o l12n_3 i/o l12p_3 i/o l11p_3 i/o l11n_3 input i/o l13n_3 vccaux vccint gnd vccint k gnd i/o l14n_3 lhclk1 i/o l14p_3 lhclk0 vccaux input vref_3 i/o l13p_3 i/o l15p_3 lhclk2 gnd vccint gnd l i/o l16n_3 lhclk5 vcco_3 i/o l17n_3 lhclk7 gnd input vcco_3 i/o l15n_3 lhclk3 irdy2 input gnd vccint m i/o l16p_3 lhclk4 t rdy2 input i/o l17p_3 lhclk6 i/o l19n_3 i/o l19p_3 i/o l20p_3 i/o l18n_3 i/o l18p_3 vccint gnd n i/o l21p_3 i/o l21n_3 i/o l23p_3 i/o l23n_3 input i/o l20n_3 vref_3 i/o l22p_3 vccint vccaux vccint p i/o l24p_3 gnd input vcco_3 i/o l25p_3 input vref_3 i/o l22n_3 i/o gnd r i/o l24n_3 i/o l26p_3 i/o l27p_3 i/o l27n_3 i/o l25n_3 gnd i/o l09n_2 vref_2 input l11n_2 i/o t i/o l28n_3 vref_3 i/o l26n_3 i/o l29n_3 input i/o l06p_2 i/o l06n_2 i/o l09p_2 input l11p_2 input l14p_2 input l14n_2 vref_2 u i/o l28p_3 vcco_3 i/o l29p_3 i/o l01p_2 cso_b i/o l03p_2 dout busy input l05p_2 i/o l07n_2 vcco_2 i/o l12n_2 vccaux v i/o l30n_3 i/o l30p_3 gnd i/o l01n_2 init_b input l05n_2 i/o l07p_2 i/o l10n_2 i/o l12p_2 w input input l02p_2 input i/o l04p_2 vcco_2 input l08p_2 gnd i/o l10p_2 i/o y gnd input l02n_2 i/o vref_2 i/o l04n_2 i/o input l08n_2 i/o i/o l13n_2 i/o l13p_2 gnd bank 0 bank 3 bank 2 gclk13 l15n_2 d6 gclk2 d2 l18p_2 i/o gclk12 l15p_2 d7 i/o gclk14 d4 l16p_2 i/o lk15 d3 l16n_2 i/o gc csi_b mosi l03n_2 i/o 9 DS312-4_08_101905 pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 223 product specification r fg400 footprint right half of package (top view) 11 12 13 14 15 16 17 18 19 20 gnd i/o i/o l09n_0 vref_0 i/o l09p_0 i/o l06n_0 i/o l04p_0 i/o l04n_0 i/o l03n_0 vref_0 i/o l03p_0 gnd a input l14n_0 input l14p_0 i/o l10n_0 gnd i/o l06p_0 vcco_0 i/o l01n_0 input tdo input b i/o vref_0 i/o l12n_0 i/o l10p_0 i/o l07n_0 input l05p_0 input l02n_0 i/o l01p_0 gnd i/o l30n_1 ldc2 i/o l30p_1 ldc1 c vccaux i/o l12p_0 vcco_0 i/o l07p_0 input l05n_0 input l02p_0 tck i/o l29n_1 ldc0 vcco_1 i/o l28n_1 d i/o l16p_0 gclk6 i/o l13n_0 i/o input l08n_0 input l08p_0 i/o tm s i/o l29p_1 hdc input vref_1 i/o l28p_1 e i/o l15p_0 gclk4 i/o l13p_0 i/o i/o gnd i/o l25p_1 i/o l27p_1 i/o l27n_1 i/o l26n_1 i/o l26p_1 f i/o l15n_0 gclk5 gnd input l11p_0 input l11n_0 input i/o l25n_1 vcco_1 input gnd i/o l24p_1 g vccint vccaux vccint input i/o l22n_1 i/o l22p_1 i/o l23p_1 i/o l23n_1 i/o l21n_1 i/o l24n_1 vref_1 h gnd vccint i/o l19n_1 a0 i/o l19p_1 input i/o l18p_1 a2 i/o l20n_1 i/o l20p_1 i/o l21p_1 j vccint gnd vcco_1 i/o l18n_1 a1 gnd input vref_1 vcco_1 k gnd vccint gnd vccaux input i/o l13n_1 vref_1 gnd l vccint gnd vccint vccaux i/o l11p_1 i/o i/o l12p_1 a12 i/o l12n_1 a11 i/o l13p_1 input m i/o d5 vccint gnd input i/o l11n_1 i/o l09p_1 vcco_1 i/o l10p_1 i/o l10n_1 input n i/o i/o l25n_2 input i/o l09n_1 i/o l07p_1 i/o l07n_1 gnd i/o l08n_1 vref_1 p vcco_2 input l20p_2 i/o i/o l25p_2 gnd input i/o l05p_1 i/o l05n_1 input i/o l08p_1 r i/o m1 input l20n_2 input l23n_2 vref_2 input l23p_2 i/o l28n_2 input i/o l02p_1 a14 i/o l02n_1 a13 vcco_1 i/o l06n_1 t gnd i/o l21n_2 i/o l24n_2 vcco_2 i/o l28p_2 i/o l30p_2 a21 i/o l01p_1 a16 i/o l01n_1 a15 i/o l03p_1 i/o l06p_1 u i/o l21p_2 i/o l24p_2 input l26n_2 input l26p_2 i/o l30n_2 a20 done gnd i/o l03n_1 vref_1 i/o l04p_1 v vcco_2 i/o l22n_2 vref_2 i/o l22p_2 gnd i/o input l29n_2 vcco_2 i/o l31p_2 vs2 a19 i/o l32n_2 cclk i/o l04n_1 w i/o l19p_2 m0 i/o l19n_2 din d0 i/o i/o l27n_2 a22 i/o l27p_2 a23 input l29p_2 i/o vref_2 i/o l31n_2 vs1 a18 i/o l32p_2 vs0 a17 gnd y bank 1 bank 2 bank 0 i/o l18n_2 d1 gc lk3 input l17p_2 rdwr_b gclk0 input l17n_2 m2 gclk1 rh c lk1 l14n_1 a9 i/o c rh lk 0 a10 l14p_1 c i/o l16p_1 a6 irdy1 rh lk4 l16n_1 a5 i/o rhclk 5 rhclk3 l15n_1 trdy1 a7 i/o i/o l15p_1 a 8 rhclk2 rhclk 6 a4 l17p_1 i/o rhclk7 a3 l17n_1 i/o DS312-4_09_101905 pinout descriptions 224 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r fg484: 484-ball fine-p itch ball grid array the 484-ball fine-pitch ball grid array, fg484, supports the xc3s1600e fpga. table 154 lists all the fg484 package pins. they are sorted by bank number and then by pin name. pairs of pins that form a differential i/o pair appear together in the table. the table also shows the pin number for each pin and the pin type, as defined earlier. an electronic version of this package pinout table and foot- print diagram is available for download from the xilinx web- site at: http://www.xilinx.com/support/doc umentation/data_sheets/s3e_pin.zip pinout table table 154: fg484 package pinout bank xc3s1600e pin name fg484 ball type 0 io b6 i/o 0 io b13 i/o 0 io c5 i/o 0 io c14 i/o 0 io e16 i/o 0 io f9 i/o 0 io f16 i/o 0 io g8 i/o 0 io h10 i/o 0 io h15 i/o 0 io j11 i/o 0 io/vref_0 g12 vref 0 io_l01n_0 c18 i/o 0 io_l01p_0 c19 i/o 0 io_l03n_0/vref_0 a20 vref 0 io_l03p_0 a21 i/o 0 io_l04n_0 a19 i/o 0 io_l04p_0 a18 i/o 0 io_l06n_0 c16 i/o 0 io_l06p_0 d16 i/o 0 io_l07n_0 a16 i/o 0 io_l07p_0 a17 i/o 0 io_l09n_0/vref_0 b15 vref 0 io_l09p_0 c15 i/o 0 io_l10n_0 g15 i/o 0 io_l10p_0 f15 i/o 0 io_l11n_0 d14 i/o 0 io_l11p_0 e14 i/o 0 io_l12n_0/vref_0 a14 vref 0 io_l12p_0 a15 i/o 0 io_l13n_0 h14 i/o 0 io_l13p_0 g14 i/o 0 io_l15n_0 g13 i/o 0 io_l15p_0 f13 i/o 0 io_l16n_0 j13 i/o 0 io_l16p_0 h13 i/o 0 io_l18n_0/gclk5 e12 gclk 0 io_l18p_0/gclk4 f12 gclk 0 io_l19n_0/gclk7 c12 gclk 0 io_l19p_0/gclk6 b12 gclk 0 io_l21n_0/gclk11 b11 gclk 0 io_l21p_0/gclk10 c11 gclk 0 io_l22n_0 d11 i/o 0 io_l22p_0 e11 i/o 0 io_l24n_0 a9 i/o 0 io_l24p_0 a10 i/o 0 io_l25n_0/vref_0 d10 vref 0 io_l25p_0 c10 i/o 0 io_l27n_0 h8 i/o 0 io_l27p_0 h9 i/o 0 io_l28n_0 c9 i/o 0 io_l28p_0 b9 i/o 0 io_l29n_0 e9 i/o 0 io_l29p_0 d9 i/o 0 io_l30n_0 b8 i/o 0 io_l30p_0 a8 i/o 0 io_l32n_0/vref_0 f7 vref 0 io_l32p_0 f8 i/o 0 io_l33n_0 a6 i/o 0 io_l33p_0 a7 i/o 0 io_l35n_0 a4 i/o 0 io_l35p_0 a5 i/o 0 io_l36n_0 e7 i/o 0 io_l36p_0 d7 i/o 0 io_l38n_0/vref_0 d6 vref 0 io_l38p_0 d5 i/o 0 io_l39n_0 b4 i/o 0 io_l39p_0 b3 i/o table 154: fg484 package pinout (continued) bank xc3s1600e pin name fg484 ball type pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 225 product specification r 0 io_l40n_0/hswap d4 dual 0 io_l40p_0 c4 i/o 0 ip b19 input 0 ip e6 input 0 ip_l02n_0 d17 input 0 ip_l02p_0 d18 input 0 ip_l05n_0 c17 input 0 ip_l05p_0 b17 input 0 ip_l08n_0 e15 input 0 ip_l08p_0 d15 input 0 ip_l14n_0 d13 input 0 ip_l14p_0 c13 input 0 ip_l17n_0 a12 input 0 ip_l17p_0 a13 input 0 ip_l20n_0/gclk9 h11 gclk 0 ip_l20p_0/gclk8 h12 gclk 0 ip_l23n_0 f10 input 0 ip_l23p_0 f11 input 0 ip_l26n_0 g9 input 0 ip_l26p_0 g10 input 0 ip_l31n_0 c8 input 0 ip_l31p_0 d8 input 0 ip_l34n_0 c7 input 0 ip_l34p_0 c6 input 0 ip_l37n_0 a3 input 0 ip_l37p_0 a2 input 0 vcco_0 b5 vcco 0 vcco_0 b10 vcco 0 vcco_0 b14 vcco 0 vcco_0 b18 vcco 0 vcco_0 e8 vcco 0 vcco_0 f14 vcco 0 vcco_0 g11 vcco 1 io_l01n_1/a15 y22 dual 1 io_l01p_1/a16 aa22 dual 1 io_l02n_1/a13 w21 dual 1 io_l02p_1/a14 y21 dual 1 io_l03n_1/vref_1 w20 vref 1 io_l03p_1 v20 i/o 1 io_l04n_1 u19 i/o 1 io_l04p_1 v19 i/o table 154: fg484 package pinout (continued) bank xc3s1600e pin name fg484 ball type 1 io_l05n_1 v22 i/o 1 io_l05p_1 w22 i/o 1 io_l06n_1 t19 i/o 1 io_l06p_1 t18 i/o 1 io_l07n_1/vref_1 u20 vref 1 io_l07p_1 u21 i/o 1 io_l08n_1 t22 i/o 1 io_l08p_1 u22 i/o 1 io_l09n_1 r19 i/o 1 io_l09p_1 r18 i/o 1 io_l10n_1 r16 i/o 1 io_l10p_1 t16 i/o 1 io_l11n_1 r21 i/o 1 io_l11p_1 r20 i/o 1 io_l12n_1/vref_1 p18 vref 1 io_l12p_1 p17 i/o 1 io_l13n_1 p22 i/o 1 io_l13p_1 r22 i/o 1 io_l14n_1 p15 i/o 1 io_l14p_1 p16 i/o 1 io_l15n_1 n18 i/o 1 io_l15p_1 n19 i/o 1 io_l16n_1/a11 n16 dual 1 io_l16p_1/a12 n17 dual 1 io_l17n_1/vref_1 m20 vref 1 io_l17p_1 n20 i/o 1 io_l18n_1/a9/rhclk1 m22 rhclk/ dual 1 io_l18p_1/a10/rhclk0 n22 rhclk/ dual 1 io_l19n_1/a7/rhclk3/ trdy1 m16 rhclk/ dual 1 io_l19p_1/a8/rhclk2 m15 rhclk/ dual 1 io_l20n_1/a5/rhclk5 l21 rhclk/ dual 1 io_l20p_1/a6/rhclk4/ irdy1 l20 rhclk/ dual 1 io_l21n_1/a3/rhclk7 l19 rhclk/ dual 1 io_l21p_1/a4/rhclk6 l18 rhclk/ dual 1 io_l22n_1/a1 k22 dual table 154: fg484 package pinout (continued) bank xc3s1600e pin name fg484 ball type pinout descriptions 226 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r 1 io_l22p_1/a2 l22 dual 1 io_l23n_1/a0 k17 dual 1 io_l23p_1 k16 i/o 1 io_l24n_1 k19 i/o 1 io_l24p_1 k18 i/o 1 io_l25n_1 k15 i/o 1 io_l25p_1 j15 i/o 1 io_l26n_1 j20 i/o 1 io_l26p_1 j21 i/o 1 io_l27n_1 j17 i/o 1 io_l27p_1 j18 i/o 1 io_l28n_1/vref_1 h21 vref 1 io_l28p_1 h22 i/o 1 io_l29n_1 h20 i/o 1 io_l29p_1 h19 i/o 1 io_l30n_1 h17 i/o 1 io_l30p_1 g17 i/o 1 io_l31n_1 f22 i/o 1 io_l31p_1 g22 i/o 1 io_l32n_1 f20 i/o 1 io_l32p_1 g20 i/o 1 io_l33n_1 g18 i/o 1 io_l33p_1 g19 i/o 1 io_l34n_1 d22 i/o 1 io_l34p_1 e22 i/o 1 io_l35n_1 f19 i/o 1 io_l35p_1 f18 i/o 1 io_l36n_1 e20 i/o 1 io_l36p_1 e19 i/o 1 io_l37n_1/ldc0 c21 dual 1 io_l37p_1/hdc c22 dual 1 io_l38n_1/ldc2 b21 dual 1 io_l38p_1/ldc1 b22 dual 1 ip d20 input 1 ip f21 input 1 ip g16 input 1 ip h16 input 1 ip j16 input 1 ip j22 input 1 ip k20 input 1 ip l15 input table 154: fg484 package pinout (continued) bank xc3s1600e pin name fg484 ball type 1 ip m18 input 1 ip n15 input 1 ip n21 input 1 ip p20 input 1 ip r15 input 1 ip t17 input 1 ip t20 input 1 ip u18 input 1 ip/vref_1 d21 vref 1 ip/vref_1 l17 vref 1 vcco_1 e21 vcco 1 vcco_1 h18 vcco 1 vcco_1 k21 vcco 1 vcco_1 l16 vcco 1 vcco_1 p21 vcco 1 vcco_1 r17 vcco 1 vcco_1 v21 vcco 2 io y8 i/o 2 io y9 i/o 2 io aa10 i/o 2 io ab5 i/o 2 io ab13 i/o 2 io ab14 i/o 2 io ab16 i/o 2 io ab18 i/o 2 io/d5 ab11 dual 2 io/m1 aa12 dual 2 io/vref_2 ab4 vref 2 io/vref_2 ab21 vref 2 io_l01n_2/init_b ab3 dual 2 io_l01p_2/cso_b aa3 dual 2 io_l03n_2/mosi/csi_b y5 dual 2 io_l03p_2/dout/busy w5 dual 2 io_l04n_2 w6 i/o 2 io_l04p_2 v6 i/o 2 io_l06n_2 w7 i/o 2 io_l06p_2 y7 i/o 2 io_l07n_2 u7 i/o 2 io_l07p_2 v7 i/o 2 io_l09n_2/vref_2 v8 vref 2 io_l09p_2 w8 i/o table 154: fg484 package pinout (continued) bank xc3s1600e pin name fg484 ball type pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 227 product specification r 2 io_l10n_2 t8 i/o 2 io_l10p_2 u8 i/o 2 io_l11n_2 ab8 i/o 2 io_l11p_2 aa8 i/o 2 io_l12n_2 w9 i/o 2 io_l12p_2 v9 i/o 2 io_l13n_2/vref_2 r9 vref 2 io_l13p_2 t9 i/o 2 io_l14n_2 ab9 i/o 2 io_l14p_2 ab10 i/o 2 io_l16n_2 u10 i/o 2 io_l16p_2 t10 i/o 2 io_l17n_2 r10 i/o 2 io_l17p_2 p10 i/o 2 io_l19n_2/d6/gclk13 u11 dual/ gclk 2 io_l19p_2/d7/gclk12 v11 dual/ gclk 2 io_l20n_2/d3/gclk15 t11 dual/ gclk 2 io_l20p_2/d4/gclk14 r11 dual/ gclk 2 io_l22n_2/d1/gclk3 w12 dual/ gclk 2 io_l22p_2/d2/gclk2 y12 dual/ gclk 2 io_l23n_2/din/d0 u12 dual 2 io_l23p_2/m0 v12 dual 2 io_l25n_2 y13 i/o 2 io_l25p_2 w13 i/o 2 io_l26n_2/vref_2 u14 vref 2 io_l26p_2 u13 i/o 2 io_l27n_2 t14 i/o 2 io_l27p_2 r14 i/o 2 io_l28n_2 y14 i/o 2 io_l28p_2 aa14 i/o 2 io_l29n_2 w14 i/o 2 io_l29p_2 v14 i/o 2 io_l30n_2 ab15 i/o 2 io_l30p_2 aa15 i/o 2 io_l32n_2 w15 i/o 2 io_l32p_2 y15 i/o 2 io_l33n_2 u16 i/o table 154: fg484 package pinout (continued) bank xc3s1600e pin name fg484 ball type 2 io_l33p_2 v16 i/o 2 io_l35n_2/a22 ab17 dual 2 io_l35p_2/a23 aa17 dual 2 io_l36n_2 w17 i/o 2 io_l36p_2 y17 i/o 2 io_l38n_2/a20 y18 dual 2 io_l38p_2/a21 w18 dual 2 io_l39n_2/vs1/a18 aa20 dual 2 io_l39p_2/vs2/a19 ab20 dual 2 io_l40n_2/cclk w19 dual 2 io_l40p_2/vs0/a17 y19 dual 2 ip v17 input 2 ip ab2 input 2 ip_l02n_2 aa4 input 2 ip_l02p_2 y4 input 2 ip_l05n_2 y6 input 2 ip_l05p_2 aa6 input 2 ip_l08n_2 ab7 input 2 ip_l08p_2 ab6 input 2 ip_l15n_2 y10 input 2 ip_l15p_2 w10 input 2 ip_l18n_2/vref_2 aa11 vref 2 ip_l18p_2 y11 input 2 ip_l21n_2/m2/gclk1 p12 dual/ gclk 2 ip_l21p_2/rdwr_b/ gclk0 r12 dual/ gclk 2 ip_l24n_2 r13 input 2 ip_l24p_2 t13 input 2 ip_l31n_2/vref_2 t15 vref 2 ip_l31p_2 u15 input 2 ip_l34n_2 y16 input 2 ip_l34p_2 w16 input 2 ip_l37n_2 aa19 input 2 ip_l37p_2 ab19 input 2 vcco_2 t12 vcco 2 vcco_2 u9 vcco 2 vcco_2 v15 vcco 2 vcco_2 aa5 vcco 2 vcco_2 aa9 vcco 2 vcco_2 aa13 vcco 2 vcco_2 aa18 vcco table 154: fg484 package pinout (continued) bank xc3s1600e pin name fg484 ball type pinout descriptions 228 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r 3 io_l01n_3 c1 i/o 3 io_l01p_3 c2 i/o 3 io_l02n_3/vref_3 d2 vref 3 io_l02p_3 d3 i/o 3 io_l03n_3 e3 i/o 3 io_l03p_3 e4 i/o 3 io_l04n_3 e1 i/o 3 io_l04p_3 d1 i/o 3 io_l05n_3 f4 i/o 3 io_l05p_3 f3 i/o 3 io_l06n_3 g5 i/o 3 io_l06p_3 g4 i/o 3 io_l07n_3 f1 i/o 3 io_l07p_3 g1 i/o 3 io_l08n_3/vref_3 g6 vref 3 io_l08p_3 g7 i/o 3 io_l09n_3 h4 i/o 3 io_l09p_3 h5 i/o 3 io_l10n_3 h2 i/o 3 io_l10p_3 h3 i/o 3 io_l11n_3 h1 i/o 3 io_l11p_3 j1 i/o 3 io_l12n_3 j6 i/o 3 io_l12p_3 j5 i/o 3 io_l13n_3/vref_3 j3 vref 3 io_l13p_3 k3 i/o 3 io_l14n_3 j8 i/o 3 io_l14p_3 k8 i/o 3 io_l15n_3 k4 i/o 3 io_l15p_3 k5 i/o 3 io_l16n_3 k1 i/o 3 io_l16p_3 l1 i/o 3 io_l17n_3 l7 i/o 3 io_l17p_3 k7 i/o 3 io_l18n_3/lhclk1 l5 lhclk 3 io_l18p_3/lhclk0 m5 lhclk 3 io_l19n_3/lhclk3/irdy2 m8 lhclk 3 io_l19p_3/lhclk2 l8 lhclk 3 io_l20n_3/lhclk5 n1 lhclk 3 io_l20p_3/lhclk4/trdy2 m1 lhclk 3 io_l21n_3/lhclk7 m4 lhclk table 154: fg484 package pinout (continued) bank xc3s1600e pin name fg484 ball type 3 io_l21p_3/lhclk6 m3 lhclk 3 io_l22n_3 n6 i/o 3 io_l22p_3 n7 i/o 3 io_l23n_3 p8 i/o 3 io_l23p_3 n8 i/o 3 io_l24n_3/vref_3 n4 vref 3 io_l24p_3 n5 i/o 3 io_l25n_3 p2 i/o 3 io_l25p_3 p1 i/o 3 io_l26n_3 r7 i/o 3 io_l26p_3 p7 i/o 3 io_l27n_3 p6 i/o 3 io_l27p_3 p5 i/o 3 io_l28n_3 r2 i/o 3 io_l28p_3 r1 i/o 3 io_l29n_3 r3 i/o 3 io_l29p_3 r4 i/o 3 io_l30n_3 t6 i/o 3 io_l30p_3 r6 i/o 3 io_l31n_3 u2 i/o 3 io_l31p_3 u1 i/o 3 io_l32n_3 t4 i/o 3 io_l32p_3 t5 i/o 3 io_l33n_3 w1 i/o 3 io_l33p_3 v1 i/o 3 io_l34n_3 u4 i/o 3 io_l34p_3 u3 i/o 3 io_l35n_3 v4 i/o 3 io_l35p_3 v3 i/o 3 io_l36n_3/vref_3 w3 vref 3 io_l36p_3 w2 i/o 3 io_l37n_3 y2 i/o 3 io_l37p_3 y1 i/o 3 io_l38n_3 aa1 i/o 3 io_l38p_3 aa2 i/o 3 ip f2 input 3 ip f5 input 3 ip g3 input 3 ip h7 input 3 ip j7 input 3 ip k2 input table 154: fg484 package pinout (continued) bank xc3s1600e pin name fg484 ball type pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 229 product specification r 3 ip k6 input 3 ip m2 input 3 ip m6 input 3 ip n3 input 3 ip p3 input 3 ip r8 input 3 ip t1 input 3 ip t7 input 3 ip u5 input 3 ip w4 input 3 ip/vref_3 l3 vref 3 ip/vref_3 t3 vref 3 vcco_3 e2 vcco 3 vcco_3 h6 vcco 3 vcco_3 j2 vcco 3 vcco_3 m7 vcco 3 vcco_3 n2 vcco 3 vcco_3 r5 vcco 3 vcco_3 v2 vcco gnd gnd a1 gnd gnd gnd a11 gnd gnd gnd a22 gnd gnd gnd b7 gnd gnd gnd b16 gnd gnd gnd c3 gnd gnd gnd c20 gnd gnd gnd e10 gnd gnd gnd e13 gnd gnd gnd f6 gnd gnd gnd f17 gnd gnd gnd g2 gnd gnd gnd g21 gnd gnd gnd j4 gnd gnd gnd j9 gnd gnd gnd j12 gnd gnd gnd j14 gnd gnd gnd j19 gnd gnd gnd k10 gnd gnd gnd k12 gnd gnd gnd l2 gnd gnd gnd l6 gnd table 154: fg484 package pinout (continued) bank xc3s1600e pin name fg484 ball type gnd gnd l9 gnd gnd gnd l13 gnd gnd gnd m10 gnd gnd gnd m14 gnd gnd gnd m17 gnd gnd gnd m21 gnd gnd gnd n11 gnd gnd gnd n13 gnd gnd gnd p4 gnd gnd gnd p9 gnd gnd gnd p11 gnd gnd gnd p14 gnd gnd gnd p19 gnd gnd gnd t2 gnd gnd gnd t21 gnd gnd gnd u6 gnd gnd gnd u17 gnd gnd gnd v10 gnd gnd gnd v13 gnd gnd gnd y3 gnd gnd gnd y20 gnd gnd gnd aa7 gnd gnd gnd aa16 gnd gnd gnd ab1 gnd gnd gnd ab12 gnd gnd gnd ab22 gnd vccaux done aa21 config vccaux prog_b b1 config vccaux tck e17 jtag vccaux tdi b2 jtag vccaux tdo b20 jtag vccaux tms d19 jtag vccaux vccaux d12 vccaux vccaux vccaux e5 vccaux vccaux vccaux e18 vccaux vccaux vccaux k14 vccaux vccaux vccaux l4 vccaux vccaux vccaux m19 vccaux vccaux vccaux n9 vccaux vccaux vccaux v5 vccaux vccaux vccaux v18 vccaux table 154: fg484 package pinout (continued) bank xc3s1600e pin name fg484 ball type pinout descriptions 230 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r user i/os by bank table 155 indicates how the 304 available user-i/o pins are distributed between the four i/o banks on the fg484 pack- age. footprint migration differences the xc3s1600e fpga is the only spartan-3e device offered in the fg484 package. vccaux vccaux w11 vccaux vccint vccint j10 vccint vccint vccint k9 vccint vccint vccint k11 vccint vccint vccint k13 vccint vccint vccint l10 vccint vccint vccint l11 vccint vccint vccint l12 vccint vccint vccint l14 vccint vccint vccint m9 vccint table 154: fg484 package pinout (continued) bank xc3s1600e pin name fg484 ball type vccint vccint m11 vccint vccint vccint m12 vccint vccint vccint m13 vccint vccint vccint n10 vccint vccint vccint n12 vccint vccint vccint n14 vccint vccint vccint p13 vccint table 154: fg484 package pinout (continued) bank xc3s1600e pin name fg484 ball type table 155: user i/os per bank for the xc3s1600e in the fg484 package package edge i/o bank maximum i/o all possible i/o pins by type i/o input dual vref (1) clk (1) to p 0 94 56 22 1 7 8 right 1 94 50 16 21 7 0 (2) bottom 2 94 45 18 24 7 0 (2) left 3 94 63 16 0 7 8 total 376 214 72 46 28 16 notes: 1. some vref and clk pins are on input pins. 2. the eight global clock pins in this bank have optional functionality during configuration and are counted in the dual column. pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 231 product specification r fg484 footprint left half of package (top view) 214 i/o: unrestricted, general-purpose user i/o 72 input: user i/o or reference resistor input for bank 46 dual: configuration pin, then possible user i/o 28 vref: user i/o or input voltage reference for bank 16 clk: user i/o, input, or clock buffer input 2 config: dedicated configuration pins 4 jtag: dedicated jtag port pins 48 gnd: ground 28 vcco: output voltage supply for bank 16 vccint: internal core supply voltage (+1.2v) 10 vccaux: auxiliary supply voltage (+2.5v) 0 n.c.: not connected figure 89: fg484 package footprint (top view) 1234567891011 a gnd input l37p_0 input l37n_0 i/o l35n_0 i/o l35p_0 i/o l33n_0 i/o l33p_0 i/o l30p_0 i/o l24n_0 i/o l24p_0 gnd b prog_b tdi i/o l39p_0 i/o l39n_0 vcco_0 i/o gnd i/o l30n_0 i/o l28p_0 vcco_0 i/o l21n_0 gclk11 c i/o l01n_3 i/o l01p_3 gnd i/o l40p_0 i/o input l34p_0 input l34n_0 input l31n_0 i/o l28n_0 i/o l25p_0 i/o l21p_0 gclk10 d i/o l04p_3 i/o l02n_3 vref_3 i/o l02p_3 i/o l40n_0 hswap i/o l38p_0 i/o l38n_0 vref_0 i/o l36p_0 input l31p_0 i/o l29p_0 i/o l25n_0 vref_0 i/o l22n_0 e i/o l04n_3 vcco_3 i/o l03n_3 i/o l03p_3 vccaux input i/o l36n_0 vcco_0 i/o l29n_0 gnd i/o l22p_0 f i/o l07n_3 input i/o l05p_3 i/o l05n_3 input gnd i/o l32n_0 vref_0 i/o l32p_0 i/o input l23n_0 input l23p_0 g i/o l07p_3 gnd input i/o l06p_3 i/o l06n_3 i/o l08n_3 vref_3 i/o l08p_3 i/o input l26n_0 input l26p_0 vcco_0 h i/o l11n_3 i/o l10n_3 i/o l10p_3 i/o l09n_3 i/o l09p_3 vcco_3 input i/o l27n_0 i/o l27p_0 i/o input l20n_0 gclk9 j i/o l11p_3 vcco_3 i/o l13n_3 vref_3 gnd i/o l12p_3 i/o l12n_3 input i/o l14n_3 gnd vccint i/o k i/o l16n_3 input i/o l13p_3 i/o l15n_3 i/o l15p_3 input i/o l17p_3 i/o l14p_3 vccint gnd vccint l i/o l16p_3 gnd input vref_3 vccaux i/o l18n_3 lhclk1 gnd i/o l17n_3 i/o l19p_3 lhclk2 gnd vccint vccint m i/o l20p_3 lhclk4 trdy2 input i/o l21p_3 lhclk6 i/o l21n_3 lhclk7 i/o l18p_3 lhclk0 input vcco_3 i/o l19n_3 lhclk3 irdy2 vccint gnd vccint n i/o l20n_3 lhclk5 vcco_3 input i/o l24n_3 vref_3 i/o l24p_3 i/o l22n_3 i/o l22p_3 i/o l23p_3 vccaux vccint gnd p i/o l25p_3 i/o l25n_3 input gnd i/o l27p_3 i/o l27n_3 i/o l26p_3 i/o l23n_3 gnd i/o l17p_2 gnd r i/o l28p_3 i/o l28n_3 i/o l29n_3 i/o l29p_3 vcco_3 i/o l30p_3 i/o l26n_3 input i/o l13n_2 vref_2 i/o l17n_2 t input gnd input vref_3 i/o l32n_3 i/o l32p_3 i/o l30n_3 input i/o l10n_2 i/o l13p_2 i/o l16p_2 u i/o l31p_3 i/o l31n_3 i/o l34p_3 i/o l34n_3 input gnd i/o l07n_2 i/o l10p_2 vcco_2 i/o l16n_2 v i/o l33p_3 vcco_3 i/o l35p_3 i/o l35n_3 vccaux i/o l04p_2 i/o l07p_2 i/o l09n_2 vref_2 i/o l12p_2 gnd w i/o l33n_3 i/o l36p_3 i/o l36n_3 vref_3 input i/o l03p_2 dout busy i/o l04n_2 i/o l06n_2 i/o l09p_2 i/o l12n_2 input l15p_2 vccaux y i/o l37p_3 i/o l37n_3 gnd input l02p_2 i/o l03n_2 input l05n_2 i/o l06p_2 i/o i/o input l15n_2 input l18p_2 a a i/o l38n_3 i/o l38p_3 i/o l01p_2 cso_b input l02n_2 vcco_2 input l05p_2 gnd i/o l11p_2 vcco_2 i/o input l18n_2 vref_2 a b gnd input i/o l01n_2 init_b i/o vref_2 i/o input l08p_2 input l08n_2 i/o l11n_2 i/o l14n_2 i/o l14p_2 i/o d5 bank 3 bank 0 bank 2 csi_b mosi gclk12 d7 l19p_2 i/o gclk13 d6 l19n_2 i/o gclk15 d3 l20n_2 i/o gclk14 d4 l20p_2 i/o DS312_10_101905 pinout descriptions 232 www.xilinx.com DS312-4 (v3.8) august 26, 2009 product specification r fg484 footprint right half of package (top view) 12 13 14 15 16 17 18 19 20 21 22 input l17n_0 input l17p_0 i/o l12n_0 vref_0 i/o l12p_0 i/o l07n_0 i/o l07p_0 i/o l04p_0 i/o l04n_0 i/o l03n_0 vref_0 i/o l03p_0 gnd a i/o l19p_0 gclk6 i/o vcco_0 i/o l09n_0 vref_0 gnd input l05p_0 vcco_0 input tdo i/o l38n_1 ldc2 i/o l38p_1 ldc1 b i/o l19n_0 gclk7 input l14p_0 i/o i/o l09p_0 i/o l06n_0 input l05n_0 i/o l01n_0 i/o l01p_0 gnd i/o l37n_1 ldc0 i/o l37p_1 hdc c vccaux input l14n_0 i/o l11n_0 input l08p_0 i/o l06p_0 input l02n_0 input l02p_0 tm s input input vref_1 i/o l34n_1 d i/o l18n_0 gclk5 gnd i/o l11p_0 input l08n_0 i/o tck vccaux i/o l36p_1 i/o l36n_1 vcco_1 i/o l34p_1 e i/o l18p_0 gclk4 i/o l15p_0 vcco_0 i/o l10p_0 i/o gnd i/o l35p_1 i/o l35n_1 i/o l32n_1 input i/o l31n_1 f i/o vref_0 i/o l15n_0 i/o l13p_0 i/o l10n_0 input i/o l30p_1 i/o l33n_1 i/o l33p_1 i/o l32p_1 gnd i/o l31p_1 g input l20p_0 gclk8 i/o l16p_0 i/o l13n_0 i/o input i/o l30n_1 vcco_1 i/o l29p_1 i/o l29n_1 i/o l28n_1 vref_1 i/o l28p_1 h gnd i/o l16n_0 gnd i/o l25p_1 input i/o l27n_1 i/o l27p_1 gnd i/o l26n_1 i/o l26p_1 input j gnd vccint vccaux i/o l25n_1 i/o l23p_1 i/o l23n_1 a0 i/o l24p_1 i/o l24n_1 input vcco_1 i/o l22n_1 a1 k vccint gnd vccint input vcco_1 input vref_1 i/o l22p_1 a2 l vccint vccint gnd i/o gnd input vccaux i/o l17n_1 vref_1 gnd m vccint gnd vccint input i/o l16n_1 a11 i/o l16p_1 a12 i/o l15n_1 i/o l15p_1 i/o l17p_1 input n vccint gnd i/o l14n_1 i/o l14p_1 i/o l12p_1 i/o l12n_1 vref_1 gnd input vcco_1 i/o l13n_1 p input l24n_2 i/o l27p_2 input i/o l10n_1 vcco_1 i/o l09p_1 i/o l09n_1 i/o l11p_1 i/o l11n_1 i/o l13p_1 r vcco_2 input l24p_2 i/o l27n_2 input l31n_2 vref_2 i/o l10p_1 input i/o l06p_1 i/o l06n_1 input gnd i/o l08n_1 t i/o l23n_2 din d0 i/o l26p_2 i/o l26n_2 vref_2 input l31p_2 i/o l33n_2 gnd input i/o l04n_1 i/o l07n_1 vref_1 i/o l07p_1 i/o l08p_1 u i/o l23p_2 m0 gnd i/o l29p_2 vcco_2 i/o l33p_2 input vccaux i/o l04p_1 i/o l03p_1 vcco_1 i/o l05n_1 v i/o l25p_2 i/o l29n_2 i/o l32n_2 input l34p_2 i/o l36n_2 i/o l38p_2 a21 i/o l40n_2 cclk i/o l03n_1 vref_1 i/o l02n_1 a13 i/o l05p_1 w i/o l25n_2 i/o l28n_2 i/o l32p_2 input l34n_2 i/o l36p_2 i/o l38n_2 a20 i/o l40p_2 vs0 a17 gnd i/o l02p_1 a14 i/o l01n_1 a15 y i/o m1 vcco_2 i/o l28p_2 i/o l30p_2 gnd i/o l35p_2 a23 vcco_2 input l37n_2 i/o l39n_2 vs1 a18 done i/o l01p_1 a16 a a gnd i/o i/o i/o l30n_2 i/o i/o l35n_2 a22 i/o input l37p_2 i/o l39p_2 vs2 a19 i/o vref_2 gnd a b bank 1 bank 0 bank 2 gclk3 d1 l22n_2 i/o gclk2 d2 l22p_2 i/o input l21n_2 gclk1 m2 gclk0 rdwr_b l21p_2 input rhclk2 a8 l19p_1 i/o l19n_1 trdy1 rhclk3 a rhclk6 a 4 l21p_1 i/o rhclk7 a3 l21n_1 i/o i/o l20p_1 a6 k4 rhcl irdy1 7 a5 l20n_1 i/o rhclk5 rhclk1 a9 l18n_1 i/o rhclk0 a10 l18p_1 i/o DS312_11_101905 pinout descriptions DS312-4 (v3.8) august 26, 2009 www.xilinx.com 233 product specification r revision history the following table shows the revision history for this document. date version revision 03/01/05 1.0 initial xilinx release. 03/21/05 1.1 added xc3s250e in the cp132 package to table 129 . corrected number of differential i/o pairs on cp132. added pinout and footprint information for the cp132, fg400, and fg484 packages. removed irdy and trdy pins from the vq100, tq144, and pq208 packages. 11/23/05 2.0 corrected title of table 153 . updated differential pair numbering for some pins in bank 0 of the fg400 package, affecting table 152 and figure 88 . pin functionality and ball assignment were not affected. added package thermal characteristics section. added package mass values to table 125 . 03/22/06 3.0 included i/o pins, not just input-only pins under the vref description in table 124 . clarified that some global clock inputs are input-only pins in ta bl e 1 2 4 . added information on the xc3s100e in the cp132 package, affecting ta bl e 1 2 9 , ta bl e 1 3 0 , ta bl e 1 3 3 , ta bl e 1 3 4 , ta b l e 1 3 6 , and figure 82 . ball a12 on the xc3s1600e in the fg320 package a full i/o pin, not an input-only pin. corrected the i/o counts for the xc3s1600e in the fg320 package, affecting ta b l e 1 2 9 , ta b l e 1 5 0 , ta bl e 1 5 1 , and figure 87 . corrected pin type for xc3s1600e balls n14 and n15 in ta bl e 1 4 8 . 05/19/06 3.1 minor text edits. 11/09/06 3.4 added package thermal data for the xc3s100e in the cp132 package to ta b l e 1 3 0 . corrected pin migration arrows for balls e17 and f4 between the xc3s500e and xc3s1600e in table 151 . promoted module 4 to production status. synchronized all modules to v3.4. 03/16/07 3.5 minor formatting changes. 05/29/07 3.6 corrected "lxx" to "lxxy" in ta b l e 1 2 4 . noted that some gclk and vref pins are on input pins in ta b l e 1 2 4 and ta bl e 1 2 9 . added link before ta bl e 1 2 7 to material declaration data sheets. 04/18/08 3.7 added xc3s500e vqg100 package. added material declaration data sheet links in ta b l e 1 2 7 . updated thermal characteristics in table 130 . updated links. 08/26/09 3.8 minor typographical updates. |
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